參數(shù)資料
型號: MC68HC705KJ1CS
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 4 MHz, MICROCONTROLLER, CDIP16
封裝: WINDOWED, CERDIP-16
文件頁數(shù): 74/108頁
文件大?。?/td> 719K
代理商: MC68HC705KJ1CS
Parallel I/O Ports (PORTS)
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
68
Freescale Semiconductor
7.3.3 Pulldown Register B
Pulldown register B inhibits the pulldown devices on port B pins programmed as inputs.
NOTE
If the SWPDI bit in the mask option register is programmed to logic 1, reset
initializes all port B pins as inputs with disabled pulldown devices.
PDIB[3:2] — Pulldown Inhibit B Bits
PDIB[3:2] disable the port B pulldown devices. Reset clears PDIB[3:2].
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
Table 7-2. Port B Pin Operation
Data Direction Bit
I/O Pin Mode
Accesses to Data Bit
Read
Write
0
Input, high-impedance
Pin
Latch(1)
1. Writing affects the data register, but does not affect input.
1
Output
Latch
Address:
$0011
Bit 7
654321
Bit 0
Read:
Write:
See Note
PDIB3
PDIB2
See Note
Reset:
000000
= Unimplemented
Note:
These pulldown devices are permanently enabled when PB5, PB4, PB1 and PB0 are con-
figured as inputs.
Figure 7-9. Pulldown Register B (PDRB)
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