參數(shù)資料
型號: MC68HC705KJ1CDWR2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁數(shù): 78/144頁
文件大?。?/td> 1377K
代理商: MC68HC705KJ1CDWR2
Memory
Mask Option Register
MC68HC705KJ1 — Rev. 2.0
Technical Data
MOTOROLA
Memory
39
SOSCD — Short Oscillator Delay Bit
The SOSCD bit controls the oscillator stabilization counter. The
normal stabilization delay following reset or exit from stop mode is
4064 tcyc. Setting SOSCD enables a 128 tcyc stabilization delay.
1 = Short oscillator delay enabled
0 = Short oscillator delay disabled
EPMSEC — EPROM Security Bit
The EPMSEC bit controls access to the EPROM/OTPROM.
1 = External access to EPROM/OTPROM denied
0 = External access to EPROM/OTPROM not denied
OSCRES — Oscillator Internal Resistor Bit
The OSCRES bit enables a 2-M
internal resistor in the oscillator
circuit.
1 = Oscillator internal resistor enabled
0 = Oscillator internal resistor disabled
NOTE:
Program the OSCRES bit to logic 0 in devices using low-speed crystal
or RC oscillators with external resistor.
SWAIT — Stop-to-Wait Conversion Bit
The SWAIT bit enables halt mode. When the SWAIT bit is set, the
CPU interprets the STOP instruction as a WAIT instruction, and the
MCU enters halt mode. Halt mode is the same as wait mode, except
that an oscillator stabilization delay of 1 to 4064 tcyc occurs after
exiting halt mode.
1 = Halt mode enabled
0 = Halt mode not enabled
SWPDI — Software Pulldown Inhibit Bit
The SWPDI bit inhibits software control of the I/O port pulldown
devices. The SWPDI bit overrides the pulldown inhibit bits in the port
pulldown inhibit registers.
1 = Software pulldown control inhibited
0 = Software pulldown control not inhibited
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