參數資料
型號: MC68HC705KJ1CDWR2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁數: 118/144頁
文件大小: 1377K
代理商: MC68HC705KJ1CDWR2
Low-Power Modes
Effects of Stop and Wait Modes
MC68HC705KJ1 — Rev. 2.0
Technical Data
MOTOROLA
Low-Power Modes
75
Exiting Wait Mode
External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
External interrupt — A high-to-low transition on the IRQ/VPP pin or
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
COP watchdog reset — A timeout of the COP watchdog resets the
MCU, starts the CPU clock, and loads the program counter with
the contents of locations $07FE and $07FF. Software can enable
timer interrupts so that the MCU periodically can exit wait mode to
reset the COP watchdog.
Timer interrupt — Real-time interrupt requests and timer overflow
interrupt requests start the MCU clock and load the program
counter with the contents of locations $07F8 and $07F9.
6.4 Effects of Stop and Wait Modes
The STOP and WAIT instructions have the following effects on MCU
modules.
6.4.1 Clock Generation
Effects of STOP and WAIT on clock generation are discussed here.
6.4.1.1 STOP
The STOP instruction disables the internal oscillator, stopping the CPU
clock and all peripheral clocks.
After exiting stop mode, the CPU clock and all enabled peripheral clocks
begin running after the oscillator stabilization delay.
NOTE:
The oscillator stabilization delay holds the MCU in reset for the first 4064
internal clock cycles.
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