參數(shù)資料
型號: MC68HC705JP7S
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP28
封裝: WINDOWED, CERAMIC, DIP-28
文件頁數(shù): 56/164頁
文件大?。?/td> 1165K
代理商: MC68HC705JP7S
Control Timing (3.0 Vdc)
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
149
15.12 Control Timing (3.0 Vdc)
Characteristic(1)
1. +2.7
≤ VDD ≤ +3.3 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
Symbol
Min
Max
Unit
Frequency of oscillation (OSC)
RC oscillator option
Crystal oscillator option
External clock source
Internal low-power oscillator
Standard product (100 kHz nominal)
Mask option (500 kHz nominal, see Note 3))
fOSC
0.1
dc
60
300
2.1
140
700
MHz
kHz
Internal operating frequency, crystal, or external clock (fOSC/2)
RC oscillator option
Crystal oscillator option
External clock source
Internal low-power oscillator
Standard product (100 kHz nominal)
Mask option (500 kHz nominal(2))
2. The 500 kHz nominal mask option is available through special order only. Contact your local Freescale sales representative
for detailed ordering information. Not offered with the RC oscillator option.
fOP
0.05
dc
30
150
1.05
70
350
MHz
kHz
Cycle time (1/fOP)
External oscillator or clock source
Internal low-power oscillator
Standard product (100 kHz nominal)
Mask option (500 kHz nominal(2))
tcyc
952
14.29
2.86
33.33
6.67
ns
s
16-bit timer
Resolution
Input capture (TCAP) pulse width
tRESL
tTH, tTL
4.0
284
tcyc
ns
Interrupt pulse width low (edge-triggered)
tILIH
284
ns
Interrupt pulse period
tILIL
(3)
3. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 21 tcyc.
tcyc
OSC1 pulse width (external clock input)
tOH, tOL
110
ns
Analog subsystem response
Voltage comparators
Switching time (10 mV overdrive, either input)
Comparator power-up delay (bias circuit already powered up)
External current source (PB0/AN0)
Switching time (IDIS to IRAMP)
Power-up delay (bias circuit already powered up)
Bias circuit power-up delay
tCPROP
tCDELAY
tISTART
tIDELAY
tBDELAY
2
1
2
s
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