參數(shù)資料
型號： MC68HC705J5A
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： 8-bit microcontroller units
中文描述： 8位微控制器單元
文件頁數(shù)： 57/106頁
文件大?。?/td> 670K
代理商： MC68HC705J5A
July 16, 1999
GENERAL RELEASE SPECIFICATION
MULTI-FUNCTION TIMER
For More Information On This Product,
Go to: www.freescale.com
REV 2.1
8-5
8.4
OPERATION DURING STOP MODE
The timer system is cleared when going into STOP mode. When STOP is exited
by an external interrupt or an LVR reset or an external RESET, the internal oscilla-
tor will resume, followed by a 224 (or 4064) internal processor oscillator stabilizing
delay. The timer system counter is then cleared and operation resumes. If chosen
by a mask option, the STOP instruction will initiate HALT mode and the effects on
the timer are as described in
Section 8.5
.
8.5
OPERATION DURING WAIT/HALT MODE
The CPU clock halts during the WAIT/HALT mode, but the timer remains active. If
interrupts are enabled, a timer interrupt or custom periodic interrupt will cause the
processor to exit the WAIT/HALT mode.
Table 8-1. RTI Rates and COP Reset Times
RT1
RT0
RTI Rates at f
OP
Freq. specified:
Divider
1MHz
Min. COP Reset at f
OP
Freq. specified:
Divider
1MHz
2MHz
2MHz
0
0
16384
16.384ms
8.192ms
131072
131ms
66ms
0
1
32768
32.768ms
16.384ms
262144
262ms
131ms
1
0
65536
65.536ms
32.768ms
524288
524ms
262ms
1
1
131072
131.072ms
65.536ms
1048576
1059ms
524ms
F
Freescale Semiconductor, Inc.
n
.
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