參數(shù)資料
型號(hào)： MC68HC705J5A
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 8-bit microcontroller units
中文描述： 8位微控制器單元
文件頁(yè)數(shù)： 41/106頁(yè)
文件大?。?/td> 670K
代理商： MC68HC705J5A
July 16, 1999
GENERAL RELEASE SPECIFICATION
LOW POWER MODES
REV 2.1
6-3
STOP Mode. The other option is for the STOP instruction to behave like a WAIT
instruction (except that the restart time will involve a delay) and place the device in
the HALT Mode.
6.1.1 STOP Mode
Execution of the STOP instruction in this mode (selected by a mask option) places
the MCU in its lowest power consumption mode. In the STOP Mode the internal
oscillator is turned off, halting all internal processing, including the COP Watchdog
Timer.
When the CPU enters STOP Mode the interrupt flags (TOF and RTIF) and the
interrupt enable bits (TOFE and RTIE) in the TCSR are cleared by internal hard-
ware to remove any pending timer interrupt requests and to disable any further
timer interrupts. Execution of the STOP instruction automatically clears the I-bit in
the Condition Code Register and sets the IRQE enable bit in the IRQ Control/Sta-
tus Register so that the IRQ external interrupt is enabled. All other registers,
including the other bits in the TCSR, and memory remain unaltered. All input/out-
put lines remain unchanged.
The MCU can be brought out of the STOP Mode only by an IRQ external interrupt
or an externally generated RESET or an LVR reset. When exiting the STOP Mode
the internal oscillator will resume after a 224 or 4064 internal processor clock
cycle oscillator stabilizing delay which is selected by a mask option.
NOTE
Execution of the STOP instruction with the STOP Mode Mask Option will cause
the oscillator to stop and therefore disable the COP Watchdog Timer. If the COP
Watchdog Timer is to be used, the STOP Mode should be changed to the HALT
Mode by choosing the appropriate mask option. See
Section 6.4
for more details.
6.1.2 HALT Mode
Execution of the STOP instruction in this mode (selected by a mask option) places
the MCU in a low-power mode, which consumes more power than the STOP
Mode. In the HALT Mode the internal processor clock is halted, suspending all
processor and internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the timer (MFT or Timer 1) or a reset to be gener-
ated from the COP Watchdog Timer. Execution of the STOP instruction automati-
cally clears the I-bit in the Condition Code Register and sets the IRQE enable bit
in the IRQ Control/Status Register so that the IRQ external interrupt is enabled.
All other registers, memory, and input/output lines remain in their previous states.
The HALT Mode may be terminated by a Timer interrupt, an external IRQ, an LVR
reset, or external RESET occurs. Since the internal timer is still running in the
HALT mode, the wake up delay timer (oscillator stabilizing delay timer) may start
counting from an unknown value. So, the internal processor clock will resume
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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