MOTOROLA
vi
MC68HC05B6
Rev. 4
TABLE OF CONTENTS
Paragraph
Number
Page
Number
TABLE OF CONTENTS
12.1.3
12.2
12.2.1
12.2.2
12.2.3
56-pin shrink dual in line package (SDIP)..................................................12–3
MC68HC05B6 mechanical dimensions...........................................................12–4
52-pin plastic leaded chip carrier (PLCC)..................................................12–4
64-pin quad flat pack (QFP).......................................................................12–5
56-pin shrink dual in line package (SDIP)..................................................12–6
13
ORDERING INFORMATION
13.1
13.2
13.3
EPROMS.........................................................................................................13–2
Verification media............................................................................................13–2
ROM verification units (RVU)...........................................................................13–2
A
MC68HC05B4
A.1
A.2
Features ........................................................................................................... A–1
Self-check mode............................................................................................... A–5
B
MC68HC05B8
B.1
Features ........................................................................................................... B–1
C
MC68HC705B5
C.1
C.2
C.2.1
C.3
C.3.1
C.4
C.5
C.5.1
C.5.2
C.5.3
C.5.4
C.5.5
C.6
C.7
Features ...........................................................................................................C–1
EPROM ............................................................................................................C–5
EPROM programming operation.................................................................C–5
EPROM registers..............................................................................................C–6
EPROM control register..............................................................................C–6
Options register (OPTR)...................................................................................C–7
Bootstrap mode................................................................................................C–8
Erased EPROM verification......................................................................C–11
EPROM parallel bootstrap load ................................................................C–11
EPROM (RAM) serial bootstrap load and execute ...................................C–13
RAM parallel bootstrap load and execute.................................................C–14
Bootstrap loader timing diagrams.............................................................C–17
DC electrical characteristics...........................................................................C–19
Control timing .................................................................................................C–19
TPG