MOTOROLA
ii
MC68HC05B6
Rev. 4
TABLE OF CONTENTS
Paragraph
Number
Page
Number
TABLE OF CONTENTS
2.5.13
2.5.14
2.5.15
2.5.16
2.5.17
2.5.18
PLMB.........................................................................................................2–13
VPP1..........................................................................................................2–13
VRH ...........................................................................................................2–13
VRL............................................................................................................2–13
PA0 – PA7/PB0 – PB7/PC0 – PC7 ............................................................2–13
PD0/AN0–PD7/AN7...................................................................................2–13
3
MEMORY AND REGISTERS
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.6
3.7
3.8
Registers ...........................................................................................................3–1
RAM ..................................................................................................................3–1
ROM..................................................................................................................3–1
Self-check ROM ................................................................................................3–2
EEPROM...........................................................................................................3–3
EEPROM control register.............................................................................3–3
EEPROM read operation.............................................................................3–5
EEPROM erase operation ...........................................................................3–5
EEPROM programming operation...............................................................3–6
Options register (OPTR)..............................................................................3–6
EEPROM during STOP mode ...........................................................................3–7
EEPROM during WAIT mode ............................................................................3–7
Miscellaneous register......................................................................................3–9
4
INPUT/OUTPUT PORTS
4.1
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.5.3.1
4.5.4
4.6
Input/output programming .................................................................................4–1
Ports A and B ....................................................................................................4–2
Port C ................................................................................................................4–3
Port D ................................................................................................................4–3
Port registers.....................................................................................................4–4
Port data registers A and B (PORTA and PORTB)......................................4–4
Port data register C (PORTC)......................................................................4–4
Port data register D (PORTD)......................................................................4–5
A/D status/control register......................................................................4–5
Data direction registers (DDRA, DDRB and DDRC)....................................4–5
Other port considerations..................................................................................4–6
TPG