參數(shù)資料
型號(hào)： MC68HC58FN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC28
封裝： PLASTIC, LCC-28
文件頁(yè)數(shù)： 44/102頁(yè)
文件大?。?/td> 700K
代理商： MC68HC58FN
MOTOROLA
DATA LINK CONTROLLER OPERATION
MC68HC58
4-2
TECHNICAL DATA
4.1.1 Power-Off Mode
Power-off mode is entered whenever the DLC digital supply voltage VDD drops below
the minimum specified value to guarantee correct DLC operation. This includes any
standby mode where the VDD supply is switched off. In this mode, the input and output
specifications of the host interface signals are not guaranteed.
4.1.2 Reset Mode
Reset mode is entered from the power-off mode whenever the DLC supply voltage
VDD rises above the minimum specified value and the DLC RST input is asserted.
Reset mode is also entered from any other mode as soon as the DLC RST is asserted.
During reset mode, the internal DLC voltage references are operative. VDD is supplied
to the internal circuits, which are held in their reset state. The internal DLC system
clock continues to run. Registers assume their reset condition. Outputs are held in
their programmed reset state, inputs and network activity are ignored.
4.1.3 Normal Mode
Normal mode is entered from the reset mode after the DLC RST is negated, and the
host loads a configuration byte into the DLC.
Normal mode is entered from the standby mode whenever network activity is sensed,
or the host reads the DLC status byte.
Normal mode is entered from the 4X mode when a BREAK symbol is received from
the J1850 bus, or the host MCU clears the 4X mode bit in the configuration register.
Normal mode is entered from block mode when the host sends the “l(fā)oad as last byte
of transmit data” command.
During normal mode, normal network operation takes place. The user should ensure
that all DLC transmissions have ceased before exiting this mode.
4.1.4 Standby Mode
Standby mode is entered when the host sends an “enter standby mode” command.
During standby mode, the DLC internal clocks are halted and the physical interface
circuitry is placed in a low power mode to await network or host activity.
4.1.5 4X Mode
4X mode is entered when the host loads the 4X mode bit configuration into the config-
uration byte.
During 4X mode, transceiver waveshaping is disabled, thus allowing the DLC to oper-
ate without any slew rate limitation. 4X mode affects only the transmitted and received
symbol timing logic of the DLC (including the digital filter).
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