M68HC16 Z SERIES
INITIALIZATION AND PROGRAMMING EXAMPLES
MOTOROLA
USER’S MANUAL
E-3
***** SRAM MODULE REGISTERS *****
RAMMCR
EQU $FB00
;RAM MODULE CONFIGURATION REGISTER
RAMTST
EQU $FB02
;RAM TEST REGISTER
RAMBAH
EQU $FB04
;RAM BASE ADDRESS HIGH REGISTER
RAMBAL
EQU $FB06
;RAM BASE ADDRESS LOW REGISTER
***** MRM MODULE REGISTERS *****
MRMCR
EQU $F820
;MASKED ROM MODULE CONFIGURATION REGISTER
ROMBAH
EQU $F824
;ROM ARRAY BASE ADDRESS REGISTER HIGH
ROMBAL
EQU $F826
;ROM ARRAY BASE ADDRESS REGISTER LOW
SIGHI
EQU $F828
;SIGNATURE REGISTER HIGH
SIGLO
EQU $F82A
;SIGNATURE REGISTER LOW
ROMBS0
EQU $F830
;ROM BOOTSTRAP WORD 0
ROMBS1
EQU $F832
;ROM BOOTSTRAP WORD 1
ROMBS2
EQU $F834
;ROM BOOTSTRAP WORD 2
ROMBS3
EQU $F836
;ROM BOOTSTRAP WORD 3
***** QSM MODULE REGISTERS *****
QMCR
EQU $FC00
;QSM MODULE CONFIGURATION REGISTER
QTEST
EQU $FC02
;QSM TEST REGISTER
QILR
EQU $FC04
;QSM INTERRUPT LEVELS REGISTER
QIVR
EQU $FC05
;QSM INTERRUPT VECTOR REGISTER
SCCR0
EQU $FC08
;SCI CONTROL REGISTER 0
SCCR1
EQU $FC0A
;SCI CONTROL REGISTER 1
SCSR
EQU $FC0C
;SCI STATUS REGISTER
SCDR
EQU $FC0E
;SCI DATA REGISTER (FULL WORD, NOT LAST 8 BITS)
QPDR
EQU $FC15
;QSM PORT DATA REGISTER
QPAR
EQU $FC16
;QSM PIN ASSIGNMENT REGISTER
QDDR
EQU $FC17
;QSM DATA DIRECTION REGISTER
SPCR0
EQU $FC18
;QSPI CONTROL REGISTER 0
SPCR1
EQU $FC1A
;QSPI CONTROL REGISTER 1
SPCR2
EQU $FC1C
;QSPI CONTROL REGISTER 2
SPCR3
EQU $FC1E
;QSPI CONTROL REGISTER 3
SPSR
EQU $FC1F
;QSPI STATUS REGISTER
RR0
EQU $FD00
;SPI REC.RAM 0
RR1
EQU $FD02
;SPI REC.RAM 1
RR2
EQU $FD04
;SPI REC.RAM 2
RR3
EQU $FD06
;SPI REC.RAM 3
RR4
EQU $FD08
;SPI REC.RAM 4
RR5
EQU $FD0A
;SPI REC.RAM 5
RR6
EQU $FD0C
;SPI REC.RAM 6
RR7
EQU $FD0E
;SPI REC.RAM 7
RR8
EQU $FD00
;SPI REC.RAM 8
RR9
EQU $FD02
;SPI REC.RAM 9
RRA
EQU $FD04
;SPI REC.RAM A
RRB
EQU $FD06
;SPI REC.RAM B
RRC
EQU $FD08
;SPI REC.RAM C
RRD
EQU $FD0A
;SPI REC.RAM D
RRE
EQU $FD0C
;SPI REC.RAM E
RRF
EQU $FD0E
;SPI REC.RAM F
TR0
EQU $FD20
;SPI TXD.RAM 0
TR1
EQU $FD22
;SPI TXD.RAM 1
TR2
EQU $FD24
;SPI TXD.RAM 2
TR3
EQU $FD26
;SPI TXD.RAM 3
TR4
EQU $FD28
;SPI TXD.RAM 4
TR5
EQU $FD2A
;SPI TXD.RAM 5
TR6
EQU $FD2C
;SPI TXD.RAM 6