
MOTOROLA
REGISTER SUMMARY
M68HC16 Z SERIES
D-58
USER’S MANUAL
D.7.7 MCCI Data Direction Register
MDDR determines whether pins configured for general-purpose I/O are inputs or out-
puts. MDDR affects both SPI function and I/O function. During reset, all MCCI pins are
configured as inputs. Table D-40 shows the effect of MDDR on MCCI pin function.
MDDR — MCCI Data Direction Register
$YFFC0A
15
8
7
6
5
4
3
2
1
0
NOT USED
DDR7
DDR6
DDR5
DDR4
DDR3
DDR2
DDR1
DDR0
RESET:
0
Table D-40 Effect of MDDR on MCCI Pin Function
MCCI Pin
Mode
MDDR Bit
Bit State
Pin Function
MISO
Master
DDR0
0
Serial data input to SPI
1
Disables data input
Slave
0
Disables data output
1
Serial data output from SPI
MOSI
Master
DDR1
0
Disables data output
1
Serial data output from SPI
Slave
0
Serial data input to SPI
1
Disables data input
SCK1
NOTES:
1. SCK is automatically assigned to the SPI whenever the SPI is enabled (when the SPE
bit in the SPCR1 is set).
Master
DDR2
—
Clock output from SPI
Slave
—
Clock input to SPI
SS
Master
DDR3
0
Assertion causes mode fault
1
General-purpose I/O
Slave
0
SPI slave-select input
1
Disables slave-select input
RXDB2
2. PMC4 and PMC6 function as general-purpose I/O pins when the corresponding RE bit
in the SCI control register (SCCR0A or SCCR0B) is cleared.
—
DDR4
0
General-purpose I/O
1
Serial data input to SCIB
TXDB3
3. PMC5 and PMC7 function as general-purpose I/O pins when the corresponding TE bit
in the SCI control register (SCCR0A or SCCR0B) is cleared.
—
DDR5
0
General-purpose I/O
1
Serial data output from SCIB
RXDA
—
DDR6
0
General-purpose I/O
1
Serial data input to SCIA
—
DDR7
0
General-purpose I/O
1
Serial data output from SCIA