參數(shù)資料
型號: MC68HC16S2CPU20
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝: TQFP-100
文件頁數(shù): 103/104頁
文件大?。?/td> 640K
代理商: MC68HC16S2CPU20
MOTOROLA
MC68HC16S2
98
MC68HC16S2TS/D
NOTES:
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
NOTES:
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
Table 48 20.97 MHz Background Debugging Mode Timing
(V
DD
and V
DDSYN
= 5.0 Vdc
±10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H)
1
Num
Characteristic
Symbol
Min
Max
Unit
B0
DSI Input Setup Time
tDSISU
15
ns
B1
DSI Input Hold Time
tDSIH
10
ns
B2
DSCLK Setup Time
tDSCSU
15
ns
B3
DSCLK Hold Time
tDSCH
10
ns
B4
DSO Delay Time
tDSOD
—25
ns
B5
DSCLK Cycle Time
tDSCCYC
2—
tcyc
B6
CLKOUT High to FREEZE Asserted/Negated
tFRZAN
—50
ns
B7
CLKOUT High to IPIPE1 High Impedance
tIFZ
—50
ns
B8
CLKOUT High to IPIPE1 Valid
tIF
—50
ns
B9
DSCLK Low Time
tDSCLO
1—
tcyc
B10
IPIPE1 High Impedance to FREEZE Asserted
tIPFA
TBD
tcyc
B11
FREEZE Negated to IPIPE[1:0] Active
tFRIP
TBD
tcyc
Table 49 25.17 MHz Background Debugging Mode Timing
(V
DD
and V
DDSYN
= 5.0 Vdc
±10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H)
1
Num
Characteristic
Symbol
Min
Max
Unit
B0
DSI Input Setup Time
tDSISU
10
ns
B1
DSI Input Hold Time
tDSIH
5—
ns
B2
DSCLK Setup Time
tDSCSU
10
ns
B3
DSCLK Hold Time
tDSCH
5—
ns
B4
DSO Delay Time
tDSOD
—20
ns
B5
DSCLK Cycle Time
tDSCCYC
2—
tcyc
B6
CLKOUT High to FREEZE Asserted/Negated
tFRZAN
—20
ns
B7
CLKOUT High to IPIPE1 High Impedance
tIFZ
—20
ns
B8
CLKOUT High to IPIPE1 Valid
tIF
—20
ns
B9
DSCLK Low Time
tDSCLO
1—
tcyc
B10
IPIPE1 High Impedance to FREEZE Asserted
tIPFA
TBD
tcyc
B11
FREEZE Negated to IPIPE[1:0] Active
tFRIP
TBD
tcyc
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