MOTOROLA
2-10
MC68HC11P2
PIN DESCRIPTIONS
2
2.6
Interrupt request (IRQ)
The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either
falling edge sensitive triggering or level sensitive triggering is program selectable (OPTION
register). IRQ is always congured to level sensitive triggering at reset.
Note:
Connect an external pull-up resistor, typically 4.7 k
, to V
DD when IRQ is used in a level
2.7
Nonmaskable interrupt (XIRQ/VPPE)
The XIRQ input provides a means of requesting a non-maskable interrupt after reset initialization.
During reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until
MCU software enables it. Because the XIRQ input is level-sensitive, it can be connected to a
multiple-source wired-OR network with an external pull-up resistor to VDD. XIRQ is often used as
a power loss detect interrupt.
Whenever XIRQ or IRQ is used with multiple interrupt sources (IRQ must be congured for level
sensitive operation if there is more than one source of IRQ interrupt), each source must drive the
interrupt input with an open-drain type of driver to avoid contention between outputs. There should
be a single pull-up resistor near the MCU interrupt input pin (typically 4.7 k
). There must also be
an interlock mechanism at each interrupt source so that the source holds the interrupt line low until
the MCU recognizes and acknowledges the interrupt request. If one or more interrupt source is
still pending after the MCU services a request, the interrupt line will still be held low and the MCU
will be interrupted again as soon as the interrupt mask bit in the MCU is cleared (normally upon
The VPPE pin is used to input the external EPROM programming voltage, which must be present
during EPROM programming.
2.8
MODA and MODB (MODA/LIR and MODB/VSTBY)
During reset, MODA and MODB select one of the four operating modes. Refer to
Section 3.After the operating mode has been selected, the LIR pin provides an open-drain output to indicate
that execution of an instruction has begun. The LIR pin is normally congured for wired-OR
operation (only pulls low). In order to detect consecutive instructions in a high-speed application,
this signal can be made to drive high for a short time to prevent false triggering. A series of E clock
cycles occurs during execution of each instruction. The LIR signal goes low during the rst E clock
cycle of each instruction (opcode fetch). This output is provided for assistance in program
debugging and its operation is controlled by the LIRDV bit in the OPT2 register.