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參數(shù)資料
| 型號： | MC68HC11KA4TS |
| 廠商： | Motorola, Inc. |
| 英文描述： | KPT 3C 3#16 PIN PLUG |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 49/68頁 |
| 文件大?。?/td> | 365K |
| 代理商： | MC68HC11KA4TS |
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MC68HC11KA4
MC68HC11KA4TS/D
MOTOROLA
49
Pins AV
DD
and AV
SS
provide the supply voltage to the digital portion of the A/D converter. Pins V
RH
and
V
RL
provide the reference supply voltage inputs.
A multiplexer allows the single A/D converter to select one of 16 analog input signals. Refer to the A/D
converter channel assignment bits CD–CA description.
The A/D converter control logic implements automatic conversion sequences on a selected channel
four times or on a group of four channels once each. A write to the ADCTL register initiates conversions
and, if made while a conversion is in process, a write to ADCTL also halts a conversion operation in
progress.
When the MULT bit is zero, the A/D converter system is configured to perform four consecutive conver-
sions on the single channel specified by the four channel-select bits (CD–CA). When the MULT bit is
one, the A/D system is configured to perform conversions on each channel in the group of four channels
specified by the CD and CC channel select bits. Refer to
Table 8
.
When the SCAN bit is zero, four conversions are performed in the desired channel group, once each,
to fill the four result registers. When SCAN is one, conversions continue channel-by-channel in the de-
sired group with the result registers being updated continually as new data becomes available.
Figure 15 Timing Diagram for a Sequence of Four A/D Conversions
Figure 16 Electrical Model of an Analog Input Pin (Sample Mode)
0
32
64
96
128 — E CYCLES
SAMPLE ANALOG INPUT
SUCCESSIVE APPROXIMATION SEQUENCE
MSB
4
CYCLES
BIT 6
2
CYC
BIT 5
2
CYC
BIT 4
2
CYC
BIT 3
2
CYC
BIT 2
2
CYC
BIT 1
2
CYC
LSB
2
CYC
2
CYC
END
R
S
CONVERT FIRST
CHANNEL, UPDATE
ADR1
CONVERT SECOND
CHANNEL, UPDATE
ADR2
CONVERT THIRD
CHANNEL, UPDATE
ADR3
CONVERT FOURTH
CHANNEL, UPDATE
ADR4
12 E CYCLES
W
E CLOCK
A/D CONVERSION TIM
DIFFUSION/POLY
COUPLER
< 2 pF
400 nA
JUNCTION
LEAKAGE
+ ~20V
– ~0.7V
*
* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.
V
RL
INPUT
+ ~12V
– ~0.7V
PROTECTION
DEVICE
≤
4 K
DUMMY N-CHANNEL
OUTPUT DEVICE
ANALOG
INPUT
PIN
~ 20 pF
DAC
CAPACITANCE
ANALOG INPUT PIN
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