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參數(shù)資料
| 型號： | MC68HC11KA4TS |
| 廠商： | Motorola, Inc. |
| 英文描述： | KPT 3C 3#16 PIN PLUG |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 26/68頁 |
| 文件大小： | 365K |
| 代理商： | MC68HC11KA4TS |
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MOTOROLA
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MC68HC11KA4
MC68HC11KA4TS/D
5 Resets and Interrupts
The MC68HC11KA4/KA2 has three reset vectors and 18 interrupt vectors. The reset vectors are as fol-
lows:
RESET, or Power-On Reset
Clock Monitor Fail
COP Failure
The 18 interrupt vectors service 22 interrupt sources (three non-maskable, 19 maskable). The three
nonmaskable interrupt vectors are as follows:
XIRQ Pin (X-Bit Interrupt)
Illegal Opcode Trap
Software Interrupt
On-chip peripheral systems generate maskable interrupts, which are recognized only if the global inter-
rupt mask bit (I) in the condition code register (CCR) is clear. Maskable interrupts are prioritized accord-
ing to a default arrangement; however, any one source can be elevated to the highest maskable priority
position by a software-accessible control register (HPRIO). The HPRIO register can be written at any
time, provided bit I in the CCR is set.
Nineteen interrupt sources in the MC68HC11KA4/KA2 are subject to masking by the global interrupt
mask bit (bit I in the CCR). In addition to the global bit I, all of these sources, except the external interrupt
(IRQ) pin, are controlled by local enable bits in control registers. Most interrupt sources in the M68HC11
have separate interrupt vectors; therefore, there is usually no need for software to poll control registers
to determine the cause of an interrupt.
For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during the
normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI system
is cleared by the automatic clearing mechanism consisting of a read of the SCI status register while
RDRF is set, followed by a read of the SCI data register. The normal response to an RDRF interrupt
request would be to read the SCI status register to check for receive errors, then to read the received
data from the SCI data register. These two steps satisfy the automatic clearing mechanism without re-
quiring any special instructions.
Refer to the following table for a list of interrupt and reset vector assignments
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC11KA4VFN2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| MC68HC11KA4VFN3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| MC68HC11KA4VFN4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| MC68HC11KA4VFU2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| MC68HC11KA4VFU3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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