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| 型號(hào)： | MC68HC11K1MFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 40/80頁 |
| 文件大?。?/td> | 420K |
| 代理商： | MC68HC11K1MFN2 |
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MOTOROLA
40
M68HC11 K Series
MC68HC11KTS/D
CME —Clock Monitor Enable
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset
FCME —Force Clock Monitor Enable
0 = Clock monitor follows the state of the CME bit
1 = Clock monitor circuit is enabled until next reset
CR[1:0] —COP Timer Rate Select
Refer to NOCOP bit in CONFIG register.
Write $55 (%01010101) to COPRST to arm COP watchdog clearing mechanism. Write $AA
(%10101010) to COPRST to reset COP watchdog. Refer to NOCOP bit in CONFIG register.
*RBOOT, SMOD, and MDA reset depend on power-up initialization mode and can only be written in special mode.
RBOOT —Read Bootstrap ROM
Refer to
2 Operating Modes
.
SMOD —Special Mode Select
Refer to
2 Operating Modes
.
MDA —Mode Select A
Refer to
2 Operating Modes
.
Table 6 COP Timer Rate Select (Timeout Period Length)
CR[1:0]
Rate
Selected
XTAL = 8.0 MHz
Timeout
–0 ms, +16.4 ms
16.384 ms
XTAL = 12.0 MHz
Timeout
–0 ms, +10.9 ms
10.923 ms
XTAL = 16.0 MHz
Timeout
–0 ms, +8.2 ms
8.192 ms
0 0
2
15
2
17
2
19
2
21
E =
0 1
65.536 ms
43.691 ms
32.768 ms
1 0
262.14 ms
174.76 ms
131.07 ms
1 1
1.049 sec
699.05 ms
524.29 ms
2.0 MHz
3.0 MHz
4.0 MHz
COPRST
—Arm/Reset COP Timer Circuitry
$003A
Bit 7
6
5
4
3
2
1
Bit 0
7
6
5
4
3
2
1
0
RESET:
0
0
0
0
0
0
0
0
HPRIO
—Highest Priority I-Bit Interrupt and Miscellaneous
$003C
Bit 7
6
5
4
3
2
1
Bit 0
RBOOT*
SMOD*
MDA*
PSEL4
PSEL3
PSEL2
PSEL1
PSEL0
RESET:
—
—
—
0
0
1
1
0
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