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參數(shù)資料
| 型號： | MC68HC11K1MFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 12/80頁 |
| 文件大?。?/td> | 420K |
| 代理商： | MC68HC11K1MFN2 |
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MOTOROLA
12
M68HC11 K Series
MC68HC11KTS/D
RBOOT — Read Bootstrap ROM/EPROM
Valid only when SMOD is set (bootstrap or special test mode). Can only be written in special modes.
0 = Bootstrap ROM disabled and not in map
1 = Bootstrap ROM enabled and in map at $BE00–$BFFF
SMOD and MDA —Special Mode Select and Mode Select A
These two bits can be read at any time. They can be written anytime in special modes. MDA can only
be written once in normal modes. SMOD cannot be set once it has been cleared.
PSEL[4:0] —Priority Select Bits [4:0]
Refer to
5 Resets and Interrupts
.
*Can be written only once in normal modes. Can be written anytime in special modes.
LIRDV —LIR Driven
In single-chip and bootstrap modes, this bit has no meaning or effect. The LIR pin is normally configured
for wired-OR operation (only pulls low). In order to detect consecutive instructions in a high-speed ap-
plication, this signal can be made to drive high for a short time to prevent false triggering.
0 = LIR not driven high out of reset
1 = LIR driven high for one quarter cycle to reduce transition time
CWOM —Port C Wired-OR Mode
Refer to
6 Parallel Input/Output
.
Bit 5 —Not implemented
Always read zero
IRVNE —Internal Read Visibility/Not E
IRVNE can be written only once in normal modes (SMOD = 0). In special modes IRVNE can be written
any time. In special test mode, IRVNE is reset to one. In all other modes, IRVNE is reset to zero.
In expanded modes this bit determines whether IRV is on or off.
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out the external data bus.
In single-chip modes this bit determines whether the E clock drives out from the chip.
0 = E is driven out from the chip.
1 = E pin is driven low. Refer to the following table.
Inputs
Latched at Reset
SMOD
0
0
1
1
MODB
1
1
0
0
MODA
0
1
0
1
Mode
Single Chip
Expanded
Bootstrap
Special Test
MDA
0
1
0
1
OPT2 —
System Configuration Options 2
$0038
Bit 7
6
5
4
3
2
1
Bit 0
LIRDV
CWOM
—
IRVNE*
LSBF
SPR2
XDV1
XDV0
RESET:
0
0
0
—
0
0
0
0
Mode
IRVNE Out
of Reset
0
0
0
1
E Clock Out
of Reset
On
On
On
On
IRV Out of
Reset
Off
Off
Off
On
IRVNE
Affects Only
E
IRV
E
IRV
IRVNE Can
Be Written
Once
Once
Anytime
Anytime
Single Chip
Expanded
Boot
Special Test
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