參數(shù)資料
型號： MC68HC11F1MFN3
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 157/162頁
文件大?。?/td> 4554K
代理商： MC68HC11F1MFN3
SERIAL COMMUNICATIONS INTERFACE
MC68HC11F1
7-8
TECHNICAL DATA
OR — Overrun Error Flag
OR is set if a new character is received before a previously received character is read
from SCDR. Clear the OR flag by reading SCSR and then reading SCDR.
0 = No overrun
1 = Overrun detected
NF — Noise Error Flag
NF is set if majority sample logic detects anything other than a unanimous decision.
Clear NF by reading SCSR and then reading SCDR.
0 = Unanimous decision
1 = Noise detected
FE — Framing Error
FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by
reading SCSR and then reading SCDR.
0 = Stop bit detected
1 = Zero detected
Bit 0 — Not implemented
Always reads zero
7.6.5 Baud Rate Register
Use this register to select different baud rates for the SCI system. The SCP[1:0] bits
select the prescaler rate for the SCR[2:0] bits. Together, these five bits provide multi-
ple baud rate combinations for a given crystal frequency. Normally, this register is writ-
ten once during initialization. The prescaler is set to its fastest rate by default out of
reset, and can be changed at any time. Refer to Table 7-1 and Table 7-2 for normal
baud rate selections.
TCLR — Clear Baud Rate Counters (Test)
SCP[1:0] — SCI Baud Rate Prescaler Selects
Refer to the SCI baud rate generator block diagram.
BAUD — Baud Rate
$102B
Bit 7
654321
Bit 0
TCLR
—
SCP1
SCP0
RCKB
SCR2
SCR1
SCR0
RESET:
00000
U
Table 7-1 Baud Rate Prescaler Selection
Prescaler
Divide Internal
Crystal Frequency (MHz)
SCP1
SCP0
Clock By
4.0
4.9152
8.0
12.0
16.0
20.0
0
1
62500
76800
125000
187500
25000
312500
0
1
3
20833
25600
41667
62500
83332
104165
1
0
4
15625
19200
31250
46875
62500
78125
1
13
4800
5907
9600
14423
19200
24000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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