參數(shù)資料
型號： MC68HC11F1CFN3R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 23/174頁
文件大?。?/td> 981K
代理商： MC68HC11F1CFN3R2
MC68HC11F1
TIMING SYSTEM
MOTOROLA
TECHNICAL DATA
9-13
The clock source for the RTI function is a free-running clock that cannot be stopped or
interrupted except by reset. This clock causes the time between successive RTI time-
outs to be a constant that is independent of the software latencies associated with flag
clearing and service. For this reason, an RTI period starts from the previous time-out,
not from when RTIF is cleared.
Every time-out causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt
request is generated. After reset, one entire RTI period elapses before the RTIF flag
is set for the first time. Refer to the TMSK2, TFLG2, and PACTL registers.
9.4.1 Timer Interrupt Mask Register 2
This register contains the real-time interrupt enable bits.
TOI — Timer Overflow Interrupt Enable
0 = TOF interrupts disabled
1 = Interrupt requested when TOF is set to one
RTII — Real-Time Interrupt Enable
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF set to one
PAOVI — Pulse Accumulator Overflow Interrupt Enable
PAII — Pulse Accumulator Input Edge
PR[1:0] — Timer Prescaler Select
Refer to Table 9-4.
NOTE
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in
TMSK2 enable the corresponding interrupt sources.
Table 9-4 RTI Rate Selection
RTR[1:0]
E = 1 MHz
E = 2 MHz
E = 3 MHz
E = 4 MHz
E = X MHz
0 0
0 1
1 0
1 1
8.192 ms
16.384 ms
32.768 ms
65.536 ms
4.096 ms
8.192 ms
16.384 ms
32.768 ms
2.731 ms
5.461 ms
10.923 ms
21.845 ms
2.048 ms
4.096 ms
8.192 ms
16.384 ms
(213/E)
(214/E)
(215/E)
(216/E)
TMSK2 — Timer Interrupt Mask Register 2
$1024
Bit 7
654321
Bit 0
TOI
RTII
PAOVI
PAII
—
PR1
PR0
RESET:
0000000
0
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