參數(shù)資料
型號： MC68HC11F1CFN3R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 170/174頁
文件大?。?/td> 981K
代理商： MC68HC11F1CFN3R2
MC68HC11F1
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
TECHNICAL DATA
7-9
RCKB — SCI Baud Rate Clock Check (Test)
SCR[2:0] — SCI Baud Rate Selects
Selects receiver and transmitter bit rate based on output from baud rate prescaler
stage. Refer to the SCI baud rate generator block diagram.
The prescaler bits, SCP[2:0], determine the highest baud rate, and the SCR[2:0] bits
select an additional binary submultiple (
≥1, ≥2, ≥4, through ≥128) of this highest baud
rate. The result of these two dividers in series is the 16X receiver baud rate clock. The
SCR[2:0] bits are not affected by reset and can be changed at any time, although they
should not be changed when any SCI transfer is in progress.
Figure 7-3 and Figure 7-4 illustrate the SCI baud rate timing chain. The prescaler se-
lect bits determine the highest baud rate. The rate select bits determine additional di-
vide by two stages to arrive at the receiver timing (RT) clock rate. The baud rate clock
is the result of dividing the RT clock by 16.
Table 7-2 Baud Rate Selection
Divide
Prescaler
Highest Baud Rate
(Prescaler Output from Previous Table)
SCR[2:0]
By
4800
19200
76800
312500
0 0 0
1
4800
19200
76800
312500
0 0 1
2
2400
9600
38400
156250
0 1 0
4
1200
4800
19200
78125
0 1 1
8
600
2400
9600
39063
1 0 0
16
300
1200
4800
19531
1 0 1
32
150
600
2400
9766
1 1 0
64
75
300
1200
4883
1 1 1
128
—
150
600
2441
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