參數(shù)資料
型號: MC68HC11ED0VFU2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 31/108頁
文件大?。?/td> 1672K
代理商: MC68HC11ED0VFU2
Central Processor Unit (CPU)
CPU Registers
MC68HC11ED0 — Rev. 1.0
Technical Summary
Central Processor Unit (CPU)
3.3.6 Condition Code Register (CCR)
This 8-bit register contains:
Five condition code indicators (C, V, Z, N, and H),
Two interrupt masking bits (IRQ and XIRQ)
A stop disable bit (S)
In the M68HC11 CPU, condition codes are updated automatically by
most instructions. For example, load accumulator A (LDAA) and store
accumulator A (STAA) instructions automatically set or clear the N, Z,
and V condition code flags. Pushes, pulls, add B to X (ABX), add B to Y
(ABY), and transfer/exchange instructions do not affect the condition
codes. Refer to Table 3-2, which shows what condition codes are
affected by a particular instruction.
3.3.6.1 Carry/Borrow (C)
The C bit is set if the arithmetic logic unit (ALU) performs a carry or
borrow during an arithmetic operation. The C bit also acts as an error flag
for multiply and divide operations. Shift and rotate instructions operate
with and through the carry bit to facilitate multiple-word shift operations.
3.3.6.2 Overflow (V)
The overflow bit is set if an operation causes an arithmetic overflow.
Otherwise, the V bit is cleared.
3.3.6.3 Zero (Z)
The Z bit is set if the result of an arithmetic, logic, or data manipulation
operation is 0. Otherwise, the Z bit is cleared. Compare instructions do
an internal implied subtraction and the condition codes, including Z,
reflect the results of that subtraction. A few operations (INX, DEX, INY,
and DEY) affect the Z bit and no other condition flags. For these
operations, only = and
≠ conditions can be determined.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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