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參數(shù)資料
| 型號(hào)： | MC68HC11ED0CFN3 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 3 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 72/108頁(yè) |
| 文件大?。?/td> | 1672K |
| 代理商： | MC68HC11ED0CFN3 |
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Technical Summary
MC68HC11ED0 — Rev. 1.0
Parallel Input/Output (I/O) Ports
Parallel Input/Output (I/O) Ports
6.3 Port A Data Register
Refer to Figure 6-1 for a description of the port A data register (PORTA).
To enable PA3 as fourth input capture, set I4/O5 bit in the pulse
accumulator control register (PACTL). Otherwise, PA3 is configured as
a fifth output compare out of reset, with bit I4/O5 being cleared. If the
DDRA3 bit in PACTL is set (configuring PA3 as an output), and IC4 is
enabled, writes to PA3 cause edges on the pin to result in input captures.
Writing to I4/O5 has no effect when the I4/O5 register is acting as IC4.
PA7 drives the pulse accumulator input but also can be configured for
general-purpose I/O or output compare. DDRA7 bit in PACTL configures
PA7 for either input or output.
NOTE:
Even when PA7 is configured as an output, the pin still drives the pulse
accumulator input.
Address:
$0000
Bit 7
6
54321
Bit 0
Read:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Write:
Reset:
U
0
UUUU
Alternate Function:
And/or:
PAI
OC1
OC2
OC1
OC3
OC1
OC4
OC1
IC4/OC5
OC1
IC1
—
IC2
—
IC3
—
U = Undefined
Figure 6-1. Port A Data Register (PORTA)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC11ED0CFU2 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Technical Summary |
| MC68HC11ED0CFU3 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Technical Summary |
| MC68HC11ED0CP2 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Technical Summary |
| MC68HC11ED0CP3 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Technical Summary |
| MC68HC11ED0MFN2 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Technical Summary |
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