
Timing System
Real-Time Interrupt (RTI)
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Timing System
157
The clock source for the RTI function is a free-running clock that cannot be stopped 
or interrupted except by reset. This clock causes the time between successive RTI 
timeouts to be a constant that is independent of the software latencies associated 
with flag clearing and service. For this reason, an RTI period starts from the 
previous timeout, not from when RTIF is cleared. 
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt 
request is generated. After reset, one entire RTI period elapses before the RTIF 
is set for the first time. Refer to the 
9.4.9 Timer Interrupt Mask 2 Register
, 
9.5.2 Timer Interrupt Flag Register 2
, and 
9.5.3 Pulse Accumulator Control 
Register
. 
9.5.1  Timer Interrupt Mask Register 2 
This register contains the real-time interrupt enable bits.
TOI — Timer Overflow Interrupt Enable Bit
0 = TOF interrupts disabled 
1 = Interrupt requested when TOF is set to 1 
RTII — Real-Time Interrupt Enable Bit
0 = RTIF interrupts disabled 
1 = Interrupt requested when RTIF set to 1 
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
Refer to 
9.7 Pulse Accumulator
. 
PAII — Pulse Accumulator Input Edge Bit
Refer to 
9.7 Pulse Accumulator
. 
Bits [3:2] — Unimplemented 
Always read 0 
PR[1:0] — Timer Prescaler Select Bits
Refer to 
Table 9-4
. 
NOTE:
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in TMSK2 enable 
the corresponding interrupt sources. 
Address:
$1024
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TOI
RTI
PAOVI
PAII
PR1
PR0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-21. Timer Interrupt Mask 2 Register (TMSK2)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
  Go to: www.freescale.com
n
.