
Central Processor Unit (CPU)
Data Sheet
M68HC11E Family — Rev. 5
86
Central Processor Unit (CPU)
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MOTOROLA
RORA
Rotate Right A
A
INH
46
—
2
—
—
—
—
RORB
Rotate Right B
B
INH
56
—
2
—
—
—
—
RTI
Return from 
Interrupt
Return from 
Subroutine
Subtract B from 
A
Subtract with 
Carry from A
See Figure 3–2
INH
3B
—
12
↓
RTS
See Figure 3–2
INH
39
—
5
—
—
—
—
—
—
—
—
SBA
A – B 
 A
INH
10
—
2
—
—
—
—
SBCA (opr)
A – M – C 
 A
A
A
A
A
A
B
B
B
B
B
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
INH
82
92
 B2
A2
A2
C2
D2
 F2
E2
E2
0D
0F
18
ii
dd
hh  ll
ff
ff
ii
dd
hh  ll
ff
ff
2
3
4
4
5
2
3
4
4
5
2
2
—
—
—
—
SBCB (opr)
Subtract with 
Carry from B
B – M – C 
 B
18
—
—
—
—
SEC
SEI
Set Carry
Set Interrupt 
Mask
Set Overflow 
Flag
Store 
Accumulator 
A
1 
 
C
1 
 I
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
1
—
SEV
1 
 V
INH
0B
—
2
—
—
—
—
—
—
1
—
STAA (opr)
A 
 M
A
A
A
A
B
B
B
B
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
INH
97
B7
 A7
 A7
D7
F7
 E7
 E7
DD
FD
 ED
 ED
CF
18
dd
hh  ll
ff
ff
dd
hh  ll
ff
ff
dd
hh  ll
ff
ff
3
4
4
5
3
4
4
5
4
5
5
6
2
—
—
—
—
0
—
STAB (opr)
Store 
Accumulator 
B
B 
 M
18
—
—
—
—
0
—
STD (opr)
Store 
Accumulator 
D
A 
 M, B 
 M + 1
18
—
—
—
—
0
—
STOP
Stop Internal 
Clocks
Store Stack 
Pointer
—
—
—
—
—
—
—
—
—
—
STS (opr)
SP 
 M : M + 1
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
9F
BF
 AF
 AF
DF
FF
 EF
 EF
DF
FF
EF
EF
80
90
 B0
A0
A0
C0
D0
 F0
E0
E0
83
93
 B3
A3
A3
18
dd
hh  ll
ff
ff
dd
hh  ll
ff
ff
dd
hh  ll
ff
ff
ii
dd
hh  ll
ff
ff
ii
dd
hh  ll
ff
ff
jj  kk
dd
hh  ll
ff
ff
4
5
5
6
4
5
5
6
5
6
6
6
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
—
—
—
—
0
—
STX  (opr)
Store Index 
Register X
IX 
 M : M + 1
CD
18
18
1A
18
—
—
—
—
0
—
STY (opr)
Store Index 
Register Y
IY 
 M : M + 1
—
—
—
—
0
—
SUBA (opr)
Subtract 
Memory from 
A 
A – M 
 A
A
A
A
A
A
A
A
A
A
A
18
—
—
—
—
SUBB (opr)
Subtract 
Memory from 
B 
B – M 
 B
18
—
—
—
—
SUBD (opr)
Subtract 
Memory from 
D 
D – M : M + 1 
 D
18
—
—
—
—
Table 4-2. Instruction Set  (Sheet 6 of 7)
Mnemonic
Operation
Description
Addressing
Mode 
Instruction
Operand
Condition Codes
H
I
Opcode
Cycles
S
X
N
Z
V
C
C
b7
b0
C
b7
b0
F
Freescale Semiconductor, Inc.
n
.