Analog-to-Digital (A/D) Converter
Conversion Process
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Analog-to-Digital (A/D) Converter
For More Information On This Product,
Go to: www.freescale.com
67
ADPU — A/D Power-Up Bit
0 = A/D powered down
1 = A/D powered up
CSEL — Clock Select Bit
0 = A/D and EEPROM use system E clock.
1 = A/D and EEPROM use internal RC clock.
IRQE — Configure IRQ for Edge-Sensitive Only Operation
Refer to
Section 5. Resets and Interrupts
.
DLY — Enable Oscillator Startup Delay Bit
0 = The oscillator startup delay coming out of stop is bypassed and the MCU
resumes processing within about four bus cycles.
1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is
started up from the stop power-saving mode. This delay allows the
crystal oscillator to stabilize.
CME — Clock Monitor Enable Bit
Refer to
Section 5. Resets and Interrupts
.
Bit 2 — Not implemented
Always reads 0
CR[1:0] — COP Timer Rate Select Bits
Refer to
Section 5. Resets and Interrupts
and
Section 9. Timing System
.
3.4 Conversion Process
The A/D conversion sequence begins one E-clock cycle after a write to the A/D
control/status register, ADCTL. The bits in ADCTL select the channel and the mode
of conversion.
An input voltage equal to V
RL
converts to $00 and an input voltage equal to V
RH
converts to $FF (full scale), with no overflow indication. For ratiometric conversions
of this type, the source of each analog input should use V
RH
as the supply voltage
and be referenced to V
RL
.
3.5 Channel Assignments
The multiplexer allows the A/D converter to select one of 16 analog signals. Eight
of these channels correspond to port E input lines to the MCU, four of the channels
are internal reference points or test functions, and four channels are reserved.
Refer to
Table 3-1
.
F
Freescale Semiconductor, Inc.
n
.