
Operating Modes and On-Chip Memory
Data Sheet
M68HC11E Family — Rev. 5
48
Operating Modes and On-Chip Memory
For More Information On This Product,
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MOTOROLA
2.3.3.1  System Configuration Register 
The system configuration register (CONFIG) consists of an EEPROM byte and 
static latches that control the startup configuration of the MCU. The contents of the 
EEPROM byte are transferred into static working latches during reset sequences. 
The operation of the MCU is controlled directly by these latches and not by 
CONFIG itself. In normal modes, changes to CONFIG do not affect operation of the 
MCU until after the next reset sequence. When programming, the CONFIG register 
itself is accessed. When the CONFIG register is read, the static latches are 
accessed. See 
2.5.1 EEPROM and CONFIG Programming and Erasure
 for 
information on modifying CONFIG.
To take full advantage of the MCU’s functionality, customers can program the 
CONFIG register in bootstrap mode. This can be accomplished by setting the 
mode pins to logic 0 and downloading a small program to internal RAM. For more 
information, Motorola application note AN1060 entitled 
M68HC11 Bootstrap 
Mode
has been included at the back of this document. The downloadable talker 
will consist of:
Bulk erase
Byte programming
Communication server
All of this functionality is provided by PCbug11 which can be found on the Motorola 
Web site at 
http://www.motorola.com/semiconductors/
. For more information 
on using PCbug11 to program an E-series device, Motorola engineering bulletin 
EB296 entitled 
Programming MC68HC711E9 Devices with PCbug11 and the 
M68HC11EVBU
 has been included at the back of this document. 
NOTE:
The CONFIG register on the 68HC11 is an EEPROM cell and must be 
programmed accordingly.
Operation of the CONFIG register in the MC68HC811E2 differs from other devices 
in the M68HC11 E series. See 
 and .
U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset, 
but the function of COP is controlled by the DISR bit in TEST1 register.
Figure 2-10. System Configuration Register (CONFIG)
Freescale Semiconductor, Inc.
.