Timing System
Computer Operating Properly (COP) Watchdog Function
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Timing System
159
9.5.3 Pulse Accumulator Control Register
Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits
control the pulse accumulator and IC4/OC5 functions.
DDRA7 — Data Direction for Port A Bit 7
Refer to
Section 6. Parallel Input/Output (I/O) Ports
.
PAEN — Pulse Accumulator System Enable Bit
Refer to
9.7 Pulse Accumulator
.
PAMOD — Pulse Accumulator Mode Bit
Refer to
9.7 Pulse Accumulator
.
PEDGE — Pulse Accumulator Edge Control Bit
Refer to
9.7 Pulse Accumulator
.
DDRA3 — Data Direction for Port A Bit 3
Refer to
Section 6. Parallel Input/Output (I/O) Ports
.
I4/O5 — Input Capture 4/Output Compare Bit
Refer to
9.7 Pulse Accumulator
.
RTR[1:0] — RTI Interrupt Rate Select Bits
These two bits determine the rate at which the RTI system requests interrupts.
The RTI system is driven by an E divided by 2
13
rate clock that is compensated
so it is independent of the timer prescaler. These two control bits select an
additional division factor. Refer to
Table 9-5
.
9.6 Computer Operating Properly (COP) Watchdog Function
The clocking chain for the COP function, tapped off of the main timer divider chain,
is only superficially related to the main timer system. The CR[1:0] bits in the
OPTION register and the NOCOP bit in the CONFIG register determine the status
of the COP function. One additional register, COPRST, is used to arm and clear
the COP watchdog reset system. Refer to
Section 5. Resets and Interrupts
for a
more detailed discussion of the COP function.
Address:
$1026
Bit 7
6
5
4
3
2
1
Bit 0
Read:
DDRA7
PAEN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 9-23. Pulse Accumulator Control Register (PACTL)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.