
Serial Peripheral Interface (SPI)
Data Sheet
M68HC11E Family — Rev. 5
138
Serial Peripheral Interface (SPI)
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MOTOROLA
8.7 SPI Registers
The three SPI registers are:
Serial peripheral control register (SPCR)
Serial peripheral status register (SPSR)
Serial peripheral data register (SPDR)
These registers provide control, status, and data storage functions.
8.7.1 Serial Peripheral Control Register
SPIE — Serial Peripheral Interrupt Enable Bit
Set the SPE bit to 1 to request a hardware interrupt sequence each time the
SPIF or MODF status flag is set. SPI interrupts are inhibited if this bit is clear or
if the I bit in the condition code register is 1.
0 = SPI system interrupts disabled
1 = SPI system interrupts enabled
SPE — Serial Peripheral System Enable Bit
When the SPE bit is set, the port D bit 2, 3, 4, and 5 pins are dedicated to the
SPI function. If the SPI is in the master mode and DDRD bit 5 is set, then the
port D bit 5 pin becomes a general-purpose output instead of the SS input.
0 = SPI system disabled
1 = SPI system enabled
DWOM — Port D Wired-OR Mode Bit
DWOM affects all port D pins.
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR — Master Mode Select Bit
It is customary to have an external pullup resistor on lines that are driven by
open-drain devices.
0 = Slave mode
1 = Master mode
Address:
$1028
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
Write:
Reset:
0
0
0
0
0
1
U
U
U = Unaffected
Figure 8-3. Serial Peripheral Control Register (SPCR)
F
Freescale Semiconductor, Inc.
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