Electrical Characteristics
MC68L11E9/E20 Peripheral Port Timing
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Electrical Characteristics
181
Figure 10-12. Port C Output Handshake Timing Diagram
Figure 10-13. 3-State Variation of Output Handshake Timing Diagram
(STRA Enables Output Buffer)
PORT C OUTPUT HNDSHK TIM
t
PWD
t
E
E
PREVIOUS PORT DATA
NEW DATA VALID
STRB (OUT)
PORT C (OUT)
WRITE PORTCL
(1)
“READY”
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
t
t
DEB
t
DEB
t
t
t
AES
STRB (IN)
STRA (IN)
Notes:
1. After reading PIOC with STAF set
E
t
DEB
t
PORT C (OUT)
(DDR = 1)
READ PORTCL
(1)
STRB (OUT)
t
PWD
t
"READY"
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
t
t
AES
OLD DATA
NEW DATA VALID
PORT C (OUT)
(DDR = 0)
STRA (IN)
a) STRA ACTIVE BEFORE PORTCL WRITE
NEW DATA VALID
PORT C (OUT)
(DDR = 0)
STRA (IN)
b) STRA ACTIVE AFTER PORTCL WRITE
t
t
DEB
t
PCZ
t
t
t
PCH
t
t
PCZ
t
t
PCH
t
PCD
t
t
PCD
t
PORT C (OUT)
PORT C (OUT)
PORT C (OUT)
Notes:
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
