Serial Peripheral Interface (SPI)
SPI Registers
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
139
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being transferred, the SCK
pin of the master device has a steady state low value. When CPOL is set, SCK
idles high. Refer to
Figure 8-2
and
8.4 Clock Phase and Polarity Controls
.
CPHA — Clock Phase Bit
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data
relationship between master and slave. The CPHA bit selects one of two
different clocking protocols. Refer to
Figure 8-2
and
8.4 Clock Phase and
Polarity Controls
.
SPR[1:0] — SPI Clock Rate Select Bits
These two bits select the SPI clock (SCK) rate when the device is configured as
master. When the device is configured as slave, these bits have no effect. Refer
to
Table 8-1
.
8.7.2 Serial Peripheral Status Register
SPIF — SPI Interrupt Complete Flag
SPIF is set upon completion of data transfer between the processor and the
external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt
is generated. To clear the SPIF bit, read the SPSR with SPIF set, then access
the SPDR. Unless SPSR is read (with SPIF set) first, attempts to write SPDR
are inhibited.
Table 8-1. SPI Clock Rates
SPR[1:0]
Divide
E Clock By
Frequency at
E = 1 MHz
(Baud)
Frequency at
E = 2 MHz
(Baud)
Frequency at
E = 3 MHz (
Baud)
Frequency at
E = 4 MHz
(Baud)
0 0
2
500 kHz
1.0 MHz
1.5 MHz
2 MHz
0 1
4
250 kHz
500 kHz
750 kHz
1 MHz
1 0
16
62.5 kHz
125 kHz
187.5 kHz
250 kHz
1 1
32
31.3 kHz
62.5 kHz
93.8 kHz
125 kHz
Address:
$1029
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SPIF
WCOL
MODF
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-4. Serial Peripheral Status Register (SPSR)
F
Freescale Semiconductor, Inc.
n
.