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| 型號(hào)： | MC68HC11D0CP2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁(yè)數(shù)： | 73/124頁(yè) |
| 文件大?。?/td> | 1481K |
| 代理商： | MC68HC11D0CP2 |
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MOTOROLA
RESETS AND INTERRUPTS
MC68HC11D3
5-8
TECHNICAL DATA
The IRVNE control bit allows internal read accesses to be available on the external
data bus during factory testing or emulation. Refer to SECTION 4 OPERATING
MODES AND ON-CHIP MEMORY for more information.
PSEL[3:0] — Priority Select Bits
These bits select one interrupt source to be elevated above all other I-bit-related
sources and can be written to only while the I bit in the CCR is set (interrupts disabled).
5.4 Interrupts
The MCU has 18 interrupt vectors that support 22 interrupt sources. The 19 maskable
interrupts are generated by on-chip peripheral systems. These interrupts are recog-
nized when the global interrupt mask bit (I) in the condition code register (CCR) is
clear. The three non-maskable interrupt sources are illegal opcode trap, software in-
terrupt, and XIRQ pin. Refer to Table 5-4, which shows the interrupt sources and vec-
tor assignments for each source.
Table 5-3 Highest Priority Interrupt Selection
PSEL[3:0]
Interrupt Source Promoted
0 0 0 0
Timer Overflow
0 0 0 1
Pulse Accumulator Overflow
0 0 1 0
Pulse Accumulator Input Edge
0 0 1 1
SPI Serial Transfer Complete
0 1 0 0
SCI Serial System
0 1 0 1
Reserved (Default to IRQ)
0 1 1 0
IRQ (External Pin)
0 1 1 1
Real-Time Interrupt
1 0 0 0
Timer Input Capture 1
1 0 0 1
Timer Input Capture 2
1 0 1 0
Timer Input Capture 3
1 0 1 1
Timer Output Compare 1
1 1 0 0
Timer Output Compare 2
1 1 0 1
Timer Output Compare 3
1 1 1 0
Timer Output Compare 4
1 1 1 1
Timer Input Capture 4/Output Compare 5
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