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參數(shù)資料
| 型號： | MC68HC11A8VCFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 86/158頁 |
| 文件大?。?/td> | 776K |
| 代理商： | MC68HC11A8VCFN2 |
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MOTOROLA
9-6
RESETS, INTERRUPTS, AND LOW POWER MODES
MC68HC11A8
TECHNICAL DATA
9
9.1.4 Clock Monitor Reset
The clock monitor function is enabled by the CME control bit in the OPTION register.
When CME is clear, the monitor function is disabled. When the CME bit is set, the
clock monitor function detects the absence of an E clock for more than a certain period
of time. The timeout period is dependent on processing parameters and will be be-
tween 5 and 100 microseconds. This means that an E-clock rate of 200 kHz or more
will never cause a clock monitor failure and an E-clock rate of 10 kHz or less will def-
initely cause a clock monitor failure. This implies that systems operating near or below
an E-clock rate of 200 kHz should not use the clock monitor function.
Upon detection of a slow or absent clock, the clock monitor circuit will cause a system
reset. This reset is issued to the external system via the bidirectional RESET pin. The
clock monitor system has a separate reset vector.
Special considerations are needed when using a STOP function and clock monitor in
the same system. Since the STOP function causes the clocks to be halted, the clock
monitor function will generate a reset sequence if it is enabled at the time the STOP
mode is entered.
The clock monitor is useful as a backup for the COP watchdog timer. Since the watch-
dog timer requires a clock to function, it will not indicate any failure if the system clocks
fail. The clock monitor would detect such a failure and force the MCU to its reset state.
Note that clocks are not required for the MCU to reach its reset configuration, although
clocks are required to sequence through reset back to the run condition.
9.1.5 Configuration Options Register (OPTION)
This is a special purpose 8-bit register that is used (optionally) during initialization to
configure internal system configuration options. With the exception of bits 7, 6, and 3
(ADPU, CSEL, and CME) which may be read or written at any time, this register may
be written to only once after a reset and thereafter is a read-only register. If no write is
performed to this location within 64 E-clock cycles after reset, then bits 5, 4, 1, and 0
(IRQE, DLY, CR1, and CR0) will become read-only to minimize the possibility of any
accidental changes to the system configuration (writes will be ignored). While in spe-
cial test modes, the protection mechanism on this register is preempted and all bits in
the OPTION register may be written repeatedly.
ADPU — A/D Power-up
This bit controls operations of the on-chip analog-to-digital converter. When ADPU is
clear, the A/D system is powered down and conversion requests will not return mean-
ingful information. To use the A/D system, this bit should be set. A 100 microsecond
delay is required after ADPU is turned on to allow the A/D system to stabilize.
7
6
5
4
3
2
0
0
1
0
$
1
039
RESET
ADPU
0
CSEL
0
IRQE
0
DLY
1
CME
0
CR1
0
CR0
0
OPTION
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相關代理商/技術參數(shù) |
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| MC68HC11A8VCFU2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
| MC68HC11AOFNR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
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