參數(shù)資料
型號(hào)： MC68HC11A8MCFN2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 97/158頁
文件大?。?/td> 776K
代理商： MC68HC11A8MCFN2
MC68HC11A8
TECHNICAL DATA
RESETS, INTERRUPTS, AND LOW POWER MODES
MOTOROLA
9-17
9
NOTE:
During reset, PSEL3, PSEL2, PSEL1, and PSEL0 are initialized to 0:1:0:1 which corresponds to “Reserved (de-
fault to IRQ)” being the highest priority I-bit-related interrupt source.
9.3 Low-Power Modes
The MCU contains two programmable low power consumption modes; WAIT and
STOP. These two instructions are discussed below.
Table 9-7
summarizes the activity
on all pins of the MCU for all operating conditions.
9.3.1 WAIT Instruction
The WAI instruction puts the MCU in a low power consumption mode, keeping the os-
cillator running. Upon execution of a WAI instruction, the machine state is stacked and
program execution stops. The wait state can be exited only by an unmasked interrupt
or RESET. If the I bit is set (interrupts masked) and the COP is disabled, the timer sys-
tem will be turned off to additionally reduce power consumption. The amount of power
savings is application dependent and depends upon circuitry connected to the MCU
pins as well as which subsystems (i.e., timer, SPI, SCI) are active when the WAIT
mode is entered. Turning off the A/D subsystem by clearing ADPU further reduces
WAIT mode current.
9.3.2 STOP Instruction
The STOP instruction places the MCU in its lowest power consumption mode provided
the S bit in the condition code register is clear. If the S bit is set, the STOP mode is
disabled and STOP instructions are treated as NOPs (no operation). In the STOP
mode, all clocks including the internal oscillator are stopped causing all internal pro-
cessing to be halted. Recovery from the STOP mode may be accomplished by RE-
SET, XIRQ, or an unmasked IRQ. When the XIRQ is used, the MCU exits from the
STOP mode regardless of the state of the X bit in the condition code register; however,
Table 9-6 Highest Priority I Interrupt versus PSEL[3:0]
PSEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PSEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
PSEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
PSEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt Source Promoted
Timer Overflow
Pulse Accumulator Overflow
Pulse Accumulator Input Edge
SPI Serial Transfer Complete
SCI Serial System
Reserved (Default to IRQ)
IRQ (External Pin or Parallel l/O)
Real Time Interrupt
Timer Input Capture 1
Timer Input Capture 2
Timer Input Capture 3
Timer Output Compare 1
Timer Output Compare 2
Timer Output Compare 3
Timer Output Compare 4
Timer Output Compare 5
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