MC68HC11A8
TECHNICAL DATA
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MOTOROLA
10-7
10
BITA (opr)
Bit(s) Test A with Memory
AM
A IMM
A DIR
A EXT
A IND,X
A IND,Y
B IMM
B DIR
B EXT
B IND,X
B IND,Y
REL
REL
REL
REL
REL
REL
REL
REL
DIR
IND,X
IND,Y
REL
DIR
IND,X
IND,Y
DIR
IND,X
IND,Y
REL
REL
REL
INH
INH
INH
EXT
IND,X
IND,Y
A INH
B INH
INH
A IMM
A DIR
A EXT
A IND,X
A IND,Y
B IMM
B DIR
B EXT
B IND,X
B IND,Y
EXT
IND,X
IND,Y
A INH
B INH
IMM
DIR
EXT
IND,X
IND,Y
85
95
B5
A5
18 A5
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
2
2
3
2
3
2
2
3
2
3
2
2
2
2
2
2
2
2
4
4
5
2
4
4
5
3
3
4
2
2
2
1
1
1
3
2
3
1
1
1
2
2
3
2
3
2
2
3
2
3
3
2
3
1
1
4
3
4
3
3
2
3
4
4
5
2
3
4
4
5
3
3
3
3
3
3
3
3
6
7
8
3
6
7
8
6
7
8
6
3
3
2
2
2
6
6
7
2
2
2
2
3
4
4
5
2
3
4
4
5
6
6
7
2
2
5
6
7
7
7
3-1
4-1
5-2
6-2
7-2
3-1
4-1
5-2
6-2
7-2
8-1
8-1
8-1
8-1
8-1
8-1
8-1
8-1
4-11
6-14
7-11
8-1
4-11
6-14 7-
11
4-10
6-13
7-10
8-2
8-1
8-1
2-1
2-1
2-1
5-8
6-3
7-3
2-1
2-1
2-1
3-1
4-1
5-2
6-2
7-2
3-1
4-1
5-2
6-2
7-2
5-8
6-3
7-3
2-1
2-1
3-5
4-9
5-11
6-11
7-8
- - - -
¤ ¤
0 -
BITB (opr)
Bit(s) Test B with Memory
BM
C5
D5
F5
E5
18 E5
- - - -
¤ ¤
0 -
BLE (rel)
BLO (rel)
BLS (rel)
BLT (rel)
BMI (rel)
BNE (rel)
BPL (rel)
BRA (rel)
BRCLR(opr)
Branch if
≤
Zero
Branch if Lower
Branch if Lower or Same
Branch If < Zero
Branch if Minus
Branch if Not = Zero
Branch if Plus
Branch Always
Branch if Bit(s) Clear
Z + (N
⊕
V) = 1
C = 1
C + Z = 1
N
⊕
V = 1
N = 1
Z = 0
N = 0
1 = 1
M mm = 0
2F rr
25 rr
23 rr
2D rr
2B rr
26 rr
2A rr
20 rr
13
1F
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
(msk)
(rel)
18 1F
dd mm rr
ff mm rr
ff mm rr
21 rr
12
1E
18 1E
ff mm rr
14
1C
18 1C
ff mm
8D rr
28 rr
29 rr
11
0C
0E
7F
6F
18 6F
ff
4F
5F
0A
81
91
B1
A1
18 A1
ff
C1
D1
F1
E1
18 E1
ff
73
63
18 63
ff
43
53
1A 83
1A 93
1A B3
1A A3
CD A3
ff
BRN (rel)
BRSET(opr)
Branch Never
Branch if Bit(s) Set
1 = 0
(M) mm = 0
- - - - - - - -
- - - - - - - -
(msk)
(rel)
dd mm rr
ff mm rr
BSET(opr)
(msk)
Set Bit(s)
M + mm
→
M
dd mm
ff mm
- - - -
¤ ¤
0 -
BSR (rel)
BVC (rel)
BVS (rel)
CBA
CLC
CLI
CLR (opr)
Branch to Subroutine
Branch if Overflow Clear
Branch if Overflow Set
Compare A to B
Clear Carry Bit
Clear Interrupt Mask
Clear Memory Byte
See Special Ops
V = 0
V = 1
A – B
0
→
C
0
→
l
0
→
M
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - -
¤ ¤ ¤ ¤
- - - - - - - 0
- - - 0 - - - -
- - - - 0 1 0 0
hh ll
ff
CLRA
CLRB
CLV
CMPA (opr) Compare A to Memory
Clear Accumulator A
Clear Accumulator B
CIear Overflow Flag
0
→
A
0
→
B
0
→
V
A – M
- - - - 0 1 0 0
- - - - 0 1 0 0
- - - - - - 0 -
- - - -
¤ ¤ ¤ ¤
ii
dd
hh ll
ff
CMPB (opr) Compare B to Memory
B – M
ii
dd
hh ll
ff
- - - -
¤ ¤ ¤ ¤
COM (opr)
1’s Complement Memory Byte $FF – M
→
M
hh ll
ff
- - - -
¤ ¤
0 1
COMA
COMB
CPD (opr)
1’s Complement A
1’s Complement B
Compare D to Memory 16-Bit
$FF – A
→
A
$FF – B
→
B
D – M:M + 1
- - - -
¤ ¤
0 1
- - - -
¤ ¤
0 1
- - - -
¤ ¤ ¤ ¤
jj kk
dd
hh ll
ff
Table 10-1 MC68HC11A8 Instructions, Addressing Modes, and Execution Times
(Sheet 2 of 6)
Source
Form(s)
Operation
Boolean Expression
Addressing
Mode for
Operand
Machine Coding
(Hexadecimal)
Opcode
B
C
Cycle
by
Cycle*
Condition Codes
Operand(s)
S X H I N Z V C
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation.
Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.