參數(shù)資料
型號: MC68HC11A8BMFN2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 21/158頁
文件大?。?/td> 1003K
代理商: MC68HC11A8BMFN2
MC68HC11A8
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MOTOROLA
TECHNICAL DATA
10-19
10
5-11
CPD, CPY
7
1
2
3
4
5
6
7
Opcode Address
Opcode Address + 1
Opcode Address + 2
Opcode Address + 3
Operand Address
Operand Address + 1
$FFFF
1
Opcode (Page Select Byte)
Opcode (Second Byte)
Operand Address (High Byte)
Operand Address (Low Byte)
Operand Data (High Byte)
Operand Data (Low Byte)
Irrelevant Data
5-12
JSR
6
1
2
3
4
5
6
Opcode Address
Opcode Address + 1
Opcode Address + 2
Subroutine Address
Stack Pointer
Stack Pointer – 1
1
0
Opcode ($BD)
Subroutine Address (High Byte)
Subroutine Address (Low Byte)
First Opcode in Subroutine
Return Address (Low Byte)
Return Address (High Byte)
Table 10-6 Cycle-by-Cycle Operation — Indexed X Mode (Sheet 1 of 2)
Reference
Number*
Address Mode
and Instructions
Cycles Cycle
#
Address Bus
R/W
Line
Data Bus
6-1
JMP
3
1
2
3
Opcode Address
Opcode Address + 1
$FFFF
1
Opcode ($6E)
Index Offset
Irrelevant Data
6-2
ADCA, ADCB, ADDA,
ADDB, ANDA, ANDB,
BITA, BITB, CMPA,
CMPB, EORA, EORB,
LDAA, LDAB, ORAA,
ORAB, SBCA, SBCB,
SUBA, SUBB
41
2
3
4
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
1
Opcode
Index Offset
Irrelevant Data
Operand Data
6-3
ASL, ASR, CLR,
COM, DEC, INC,
LSL, LSR, NEG,
ROL, ROR
61
2
3
4
5
6
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
$FFFF
(IX) + Offset
1
0
Opcode
Index Offset
Irrelevant Data
Original Operand Data
Irrelevant Data
Result Operand Data
6-4
TST
6
1
2
3
4
5
6
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
$FFFF
1
Opcode ($6D)
Index Offset
Irrelevant Data
Original Operand Data
Irrelevant Data
6-5
STAA, STAB
4
1
2
3
4
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
1
0
Opcode
Index Offset
Irrelevant Data
Accumulator Data
6-6
LDD, LDS, LDX
5
1
2
3
4
5
Opcode Address
Opcode Address + 1
$FFFF
(IX) + Offset
(IX) + Offset + 1
1
Opcode
Index Offset
Irrelevant Data
Operand Data (High Byte)
Operand Data (Low Byte)
*The reference number is given to provide a cross-reference to Table 10-1.
Table 10-5 Cycle-by-Cycle Operation — Extended Mode (Sheet 2 of 2)
Reference
Number*
Address Mode
and Instructions
Cycles Cycle
#
Address Bus
R/W
Line
Data Bus
*The reference number is given to provide a cross-reference to Table 10-1.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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