參數(shù)資料
型號: MC68HC11A8BMFN2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 111/158頁
文件大?。?/td> 1003K
代理商: MC68HC11A8BMFN2
MOTOROLA
SERIAL COMMUNICATIONS INTERFACE
MC68HC11A8
5-12
TECHNICAL DATA
5
RCKB — SCI Baud Rate Clock Check (Test)
This bit is used during factory testing to enable the exclusive-OR of the receiver clock
and transmitter clock to be driven out the TxD pin. RCKB is zero and cannot be set
while in normal operating modes.
The diagram shown in Figure 5-7 and the data given in Table 5-3 and Table 5-4 illus-
trate the divider chain used to obtain the baud rate clock. Note that there is a fixed rate
divide-by-16 between the receive clock (RT) and the transmit clock (Tx). The actual
divider chain is controlled by the combined SCP[1:0] and SCR[2:0] bits in the baud rate
register as illustrated.
Figure 5-7 Rate Generator Division
Table 5-2 Second Prescaler Stage
SCR2
SCR1
SCR0
Prescaler Output
Divide By
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
Table 5-3 Prescaler Highest Baud Rate Frequency Output
SCP Bit
Clock*
Divided
By
Crystal Frequency (MHz)
1
0
12.0
8.3886
8.0
4.9152
4.0
3.6864
0
1
187.50 K Baud
131.072 K Baud 125.000 K Baud 76.80 K Baud
62.50 K Baud 57.60 K Baud
0
1
3
62.50 K Baud
43.690 K Baud
41.666 K Baud
25.60 K Baud 20.833 K Baud 19.20 K Baud
1
0
4
46.875 K Baud
32.768 K Baud
31.250 K Baud
19.20 K Baud 15.625 K Baud 14.40 K Baud
1
13
14.423 K Baud
10.082 K Baud
9600 Baud
5.907 K Baud
4800 Baud
4430 Baud
*The clock in the “Clock Divided By” column is the internal processor clock
÷ 4
SCI BAUD DIV
OSCILLATOR
FREQUENCY
SCI TRANSMITTER
CLOCK
SCI RECEIVER
CLOCK
INTERNAL BUS
CLOCK (PH2)
SCI
PRESCALER
SCP[1:0]
SCI BAUD
SELECT
SCR[2:0]
÷ 16
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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