參數(shù)資料
型號(hào)： MC68HC11A8BCFU2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 62/158頁
文件大小： 776K
代理商： MC68HC11A8BCFU2
MOTOROLA
6-4
SERIAL PERIPHERAL INTERFACE
MC68HC11A8
TECHNICAL DATA
6
Figure 6-3
illustrates the MOSI, MISO, SCK, and SS master-slave interconnections.
Due to data direction register control of SPI outputs and the port D wire-OR mode
(DWOM) option, the SPI system can be configured in a variety of ways. Systems with
a single bidirectional data path rather than separate MISO and MOSI paths can be ac-
commodated. Since MC68HC11A8 SPI slaves can selectively disable their MISO out-
put, a broadcast message protocol is also possible.
Figure 6-3 Serial Peripheral Interface Master-Slave Interconnection
6.4 SPI Registers
There are three registers in the serial peripheral interface which provide control, sta-
tus, and data storage functions. These registers are called the serial peripheral control
register (SPCR), serial peripheral status register (SPSR), and serial peripheral data l/
O register (SPDR) and are described in the following paragraphs.
6.4.1 Serial Peripheral Control Register (SPCR)
SPIE — Serial Peripheral Interrupt Enable
0 = SPIF interrupts disabled
1 = SPI interrupt if SPIF = 1
SPE — Serial Peripheral System Enable
0 = SPI system off
1 = SPI system on
DWOM — Port D Wire-OR Mode Option
DWOM affects all six port D pins together.
0 = Port D outputs are normal CMOS outputs
1 = Port D outputs act as open-drain outputs
7
6
5
4
3
2
1
0
$
1
028
RESET
SPIE
0
SPE
0
DWOM
0
MSTR
0
CPOL
0
CPHA
1
SPR1
U
SPR0
U
SPCR
MASTER
SLAVE
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MISO
MOSI
MISO
MOSI
SCK
SCK
SS
SS
SPI CLOCK
GENERATOR
+5V
DUAL-MCU SPI CONN
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