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參數(shù)資料
| 型號： | MC68HC11A8BCFU2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 19/158頁 |
| 文件大小： | 776K |
| 代理商： | MC68HC11A8BCFU2 |
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MC68HC11A8
TECHNICAL DATA
SIGNAL DESCRIPTIONS AND OPERATING MODES
MOTOROLA
2-3
2
2.1.4 E Clock Output (E)
This is the output connection for the internally generated E clock which can be used
as a timing reference. The frequency of the E clock output is actually one fourth that
of the input frequency at the XTAL and EXTAL pins. When the E clock output is low
an internal process is taking place and, when high, data is being accessed. The E
clock signal is halted when the MCU is in STOP mode.
2.1.5 Interrupt Request (IRQ)
The IRQ input provides a means for requesting asynchronous interrupts to the
MC68HC11A8. It is program selectable (OPTION register) with a choice of either neg-
ative edge-sensitive or level-sensitive triggering, and is always configured to level-
sensitive triggering by reset. The IRQ pin requires an external pull-up resistor to V
DD
(typically 4.7K ohm).
2.1.6 Non-Maskable Interrupt (XIRQ)
This input provides a means for requesting a non-maskable interrupt, after reset ini-
tialization. During reset, the X bit in the condition code register is set and any interrupt
is masked until MCU software enables it. The XIRQ input is level sensitive and re-
quires an external pull-up resistor to V
DD
.
2.1.7 Mode A/Load Instruction Register and Mode B/Standby Voltage (MODA/LIR,
MODB/V
STBY
)
During reset, MODA and MODB are used to select one of the four operating modes.
Refer to
Table 2-1
. Paragraph
2.2 Operating Modes
provides additional information.
After the operating mode has been selected, the LIR pin provides an open-drain output
to indicate that an instruction is starting. All instructions are made up of a series of E
clock cycles. The LIR signal goes low during the first E clock cycle of each instruction
(opcode fetch). This output is provided as an aid in program debugging.
The V
STBY
signal is used as the input for RAM standby power. When the voltage on
this pin is more than one MOS threshold (about 0.7 volts) above the V
DD
voltage, the
internal 256-byte RAM and part of the reset logic are powered from this signal rather
than the V
DD
input. This allows RAM contents to be retained without V
DD
power applied
to the MCU. Reset must be driven low before V
DD
is removed and must remain low
until V
DD
has been restored to a valid level.
Table 2-1 Operating Modes vs. MODA and MODB
MODB
1
1
0
0
MODA
0
1
0
1
Mode Selected
Single Chip
Expanded Multiplexed
Special Bootstrap
Special Test
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相關(guān)代理商/技術(shù)參數(shù) |
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