參數(shù)資料
型號(hào)： MC68HC11A1VFU2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, 2 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 67/158頁
文件大?。?/td> 503K
代理商： MC68HC11A1VFU2
MC68HC11A8
TECHNICAL DATA
ANALOG-TO-DIGITAL CONVERTER
MOTOROLA
7-3
7
7.5 Operation in STOP and WAIT Modes
If a conversion sequence is still in process when either the STOP or WAIT mode is
entered, the conversion of the current channel is suspended. When the MCU resumes
normal operation, that channel will be re-sampled and the conversion sequence re-
sumed. As the MCU exits the WAIT mode, the A/D circuits are stable and valid results
can be obtained on the first conversion. However, in STOP mode, all analog bias cur-
rents are disabled and it becomes necessary to allow a stabilization period when leav-
ing the STOP mode. If the STOP mode is exited with a delay, there will be enough time
for these circuits to stabilize before the first conversion. If the STOP mode is exited
with no delay (DLY bit in OPTION register equal to zero), sufficient time must be al-
lowed for the A/D circuitry to stabilize to avoid invalid results (see
7.8 A/D Power-Up
and Clock Select
).
7.6 A/D Control/Status Register (ADCTL)
All bits in this register may be read or written, except bit 7 which is a read-only status
indicator and bit 6 which always reads as a zero.
CCF — Conversions Complete Flag
This read-only status indicator is set when all four A/D result registers contain valid
cleared to zero and a conversion sequence is started. In the continuous modes, con-
versions continue in a round-robin fashion and the result registers continue to be up-
dated with current data even though the CCF bit remains set.
NOTE
The user must write to register ADCTL to initiate conversion. To abort
a conversion in progress, write to the ADCTL register and a new con-
version sequence is initiated immediately.
Bit 6 — Not Implemented
This bit always reads zero.
SCAN — Continuous Scan Control
When this control bit is clear, the four requested conversions are performed once to
fill the four result registers. When this control bit is set, conversions continue in a
round-robin fashion with the result registers being updated as data becomes available.
MULT — Multiple-Channel/Single Channel Control
When this bit is clear, the A/D system is configured to perform four consecutive con-
versions on the single channel specified by the four channel select bits CD through CA
(bits [3:0] of the ADCTL register). When this bit is set, the A/D system is configured to
perform a conversion on each of four channels where each result register corresponds
to one channel.
7
6
0
0
5
4
3
2
1
0
CA
U
$
1
030
RESET
CCF
0
SCAN
U
MULT
U
CD
U
CC
U
CB
U
ADCTL
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