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參數(shù)資料
| 型號： | MC68HC11A1VFU2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 49/158頁 |
| 文件大小： | 503K |
| 代理商： | MC68HC11A1VFU2 |
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MC68HC11A8
TECHNICAL DATA
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
5-5
5
5.6 Transmit Data (TxD)
Transmit data is the serial data from the internal data bus which is applied through the
serial communications interface to the output line. The transmitter generates a bit time
by using a derivative of the RT clock, thus producing a transmission rate equal to 1/16
that of the receiver sample clock.
5.7 Functional Description
A block diagram of the SCI is shown in
Figure 5-6
. The user has option bits in serial
communications control register 1 (SCCR1) to determine the “wake-up” method
(WAKE bit) and data word length (M bit) of the SCI. Serial communications control reg-
ister 2 (SCCR2) provides control bits which individually enable/disable the transmitter
or receiver (TE and RE, respectively), enable system interrupts (TIE, TCIE, ILIE) and
provide the wake-up enable bit (RWU) and the send break code bit (SBK). The baud
rate register (BAUD) bits allow the user to select different baud rates which may be
used as the rate control for the transmitter and receiver.
Data transmission is initiated by a write to the serial communications data register
(SCDR). Provided the transmitter is enabled, data stored in the SCDR is transferred
to the transmit data shift register. This transfer of data sets the TDRE bit of the SCI
status register (SCSR) and may generate an interrupt if the transmit interrupt is en-
abled. The transfer of data to the transmit data shift register is synchronized with the
bit rate clock (
Figure 5-7
). All data is transmitted LSB first. Upon completion of data
transmission, the transmission complete (TC) bit of the SCSR is set (provided no
pending data, preamble, or break is to be sent), and an interrupt may be generated if
the transmit complete interrupt is enabled. If the transmitter is disabled, and the data,
preamble, or break (in the transmit shift register) has been sent, the TC bit will also be
set. This will also generate an interrupt if the TCIE bit is set. If the transmitter is dis-
abled in the middle of a transmission, that character will be completed before the trans-
mitter gives up control of the TxD pin.
When the SCDR is read, it contains the last data byte received, provided that the re-
ceiver is enabled. The RDRF bit of the SCSR is set to indicate that a data byte has
been transferred from the input serial shift register to the SCDR, which can cause an
interrupt if the receiver interrupt is enabled. The data transfer from the input serial shift
register to the SCDR is synchronized by the receiver bit rate clock. The OR (over-run),
NF (noise), or FE (framing) error bits of the SCSR may be set if data reception errors
occurred.
An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit
(which detects idle line transmission) of SCSR is set. This allows a receiver that is not
in the wake-up mode to detect the end of a message, the preamble of a new message,
or to resynchronize with the transmitter. A valid character must be received before the
idle line condition or the IDLE bit will not be set and an idle line interrupt will not be
generated.
5.8 SCI Registers
There are five registers used in the serial communications interface and the operation
of these registers is discussed in the following paragraphs. Reference should be made
to the block diagram shown in
Figure 5-6
.
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| MC68HC11A1VP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontrollers |
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| MC68HC11A8BCFU2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
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