參數(shù)資料
型號： MC68HC11A0CFU2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 6/158頁
文件大?。?/td> 3803K
代理商： MC68HC11A0CFU2
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MOTOROLA
TECHNICAL DATA
10-5
10
10.2.7 Prebyte
In order to expand the number of instructions used in the MC68HC11A8, a prebyte in-
struction has been added to certain instructions. The instructions affected are usually
associated with index register Y. The instruction opcodes which do not require a pre-
byte could be considered as page 1 of the overall opcode map. The remaining op-
codes could be considered as pages 2, 3, and 4 of the opcode map and would require
a prebyte; $18 for page 2, $1A for page 3, and $CD for page 4.
10.3 Instruction Set
The central processing unit (CPU) in the MC68HC11A8 is basically a proper extension
of the MC6801 CPU. In addition to its ability to execute all M6800 and M6801 instruc-
tions, the MC68HC11A8 CPU has a paged operation code (opcode) map with a total
of 91 new opcodes. Major functional additions include a second 16-bit index register
(Y register), two types of 16-by-16 divide instructions, STOP and WAIT instructions,
and bit manipulation instructions.
Table 10-1 shows all MC68HC11A8 instructions in all possible addressing modes. For
each instruction, the operand construction is shown as well as the total number of ma-
chine code bytes and execution time in CPU E-clock cycles. Notes are provided at the
end of Table 10-1 which explain the letters in the Operand and Execution Time col-
umns for some instructions. Definitions of “Special Ops” found in the Boolean Expres-
sion column are found in Figure 10-2.
Table 10-2 through Table 10-8 provide a detailed description of the information
present on the address bus, data bus, and the read/write (R/W) line during each cycle
of each instruction. The information is useful in comparing actual with expected results
during debug of both software and hardware as the program is executed. The informa-
tion is categorized in groups according to addressing mode and number of cycles per
instruction. In general, instructions with the same address mode and number of cycles
execute in the same manner. Exceptions are indicated in the table.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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