
Revision History
MC68HC908KX8 MC68HC908KX2 MC68HC08KX8 Data Sheet, Rev. 2.1
4
Freescale Semiconductor
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
Revision
Level
Description
Page
Number(s)
April,
2001
0.1
Label for pin 9 corrected in Figure 1-1 and Figure 1-2
19, 20
$FF is the erase state of the FLASH, not $00.
82, 252, 255
First bulleted paragraph under the subsection 15.5 Interrupts reworded
for clarity
177
Revision to the description of the CHxMAX bit and the note that follows
that description
183
Forced monitor mode information added to Table 16-1.
192
In Figure 16-10. Monitor Data Format, resistor value for connection
between VTST and IRQ1 changed from 10 k
to 1 k.
194
February,
2002
1.0
7.2 Features — Corrected third bullet
71
7.7.3 ICG Trim Register — Corrected description of the TRIM7:TRIM0
bits
97
14.2 Features — Corrected divide by factors in first bullet
165
Figure 14-1. Timebase Block Diagram — Corrected
divide-by-2 blocks
166
Table 14-1. Timebase Divider Selection — Corrected last divider tap
entry
167
Section 15. Timer Interface Module (TIM) — Timer discrepancies
corrected throughout this section
169
17.4 Thermal Characteristics — Corrected SOIC thermal resistance and
maximum junction temperature
202
17.5 5.0-Vdc DC Electrical Characteristics and — Corrected footnote
for VDD supply current in stop mode
203 and 204
Appendix B. MC68HC08KX8 — Added to supply exception information
for the MC68HC08KX8
215
March,
2004
2.0
Reformatted to current publication standards
Throughout
2.7 FLASH Page Erase Operation — Updated procedure
33
2.8 FLASH Mass Erase Operation — Updated procedure
33
2.9 FLASH Program/Read Operation — Updated procedure
34
Figure 5-1. COP Block Diagram — Updated figure
53
Table 6-1. Instruction Set Summary — Added WAIT instruction
69
Section 7. Internal Clock Generator Module (ICG) — Updated with new
information
71 through 98
14.2 Features — Corrected values given in the first bullet
165
Table 15-3. Mode, Edge, and Level Selection — Reworked for clarity
182
17.11 Memory Characteristics — Updated table with new information
210
July,
2005
2.1
Updated to meet Freescale identity guidelines.
Throughout