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5V DC Electrical Characteristics
MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1
Freescale Semiconductor
187
17.5 5V DC Electrical Characteristics
Table 17-4. DC Electrical Characteristics (5V)
Characteristic(1)
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
Symbol
Min
Typ(2)
2. Typical values reflect average measurements at midpoint of voltage range, 25
°C only.
Max
Unit
Output high voltage (ILOAD = –2.0mA)
PTA0–PTA7, PTB0–PTB7, PTD0–PTD7, PTE0–PTE1
VOH
VDD–0.8
——
V
Output low voltage (ILOAD = 1.6mA)
PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5,
PTE0–PTE1
VOL
——
0.4
V
Output low voltage (ILOAD = 25mA)
PTD6, PTD7
VOL
——
0.5
V
LED drives (VOL = 3V)
PTA0–PTA5, PTA7, PTD2, PTD3, PTD6, PTD7
IOL
10
16
25
mA
Input high voltage
PTA0–PTA7, PTB0–PTB7, PTD0–PTD7, PTE0–PTE1, RST,
IRQ, OSC1
VIH
0.7
× V
DD
—
VDD
V
Input low voltage
PTA0–PTA7, PTB0–PTB7, PTD0–PTD7, PTE0–PTE1, RST,
IRQ, OSC1
VIL
VSS
—
0.3
× V
DD
V
VDD supply current, fOP = 8MHz
Run(3)
XTAL oscillator option
RC oscillator option
Wait(4)
XTAL oscillator option
RC oscillator option
Stop(5) (–40
°C to 125°C)
XTAL oscillator option
RC oscillator option
3. Run (operating) IDD measured using external square wave clock source (fOP = 8MHz). All inputs 0.2V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 8MHz). All inputs 0.2V from rail. No dc loads. Less than
100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD.
5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
IDD
—
7.5
11
3
3.5
1.5
0.5
10
13
5.5
6
8
3
mA
A
Digital I/O ports Hi-Z leakage current
IIL
——
± 10
A
Input current
IIN
——
± 1
A
Capacitance
Ports (as input or output)
COUT
CIN
—
12
8
pF
POR rearm voltage(6)
6. Maximum is highest voltage that POR is guaranteed.
VPOR
0—
100
mV
POR rise time ramp rate(7)
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached.
RPOR
0.035
—
V/ms
Monitor mode entry voltage
VTST
1.5
× V
DD
—8.5
V
Pullup resistors(8)
PTD6, PTD7
RST, IRQ, PTA0–PTA7
8. RPU1 and RPU2 are measured at VDD = 5.0V.
RPU1
RPU2
1.8
16
3.3
26
4.8
36
k
k
Low-voltage inhibit, trip falling voltage
VTRIPF
3.60
4.25
4.48
V
Low-voltage inhibit, trip rising voltage
VTRIPR
3.75
4.40
4.63
V