Advance Information
MC68HC08AS20
—
Rev. 4.1
90
Freescale Semiconductor
8.8
8.8.1
8.8.2
Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.9
CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .111
8.10
8.10.1
8.10.2
8.10.3
8.10.4
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .111
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . .111
Parametric Influences on Reaction Time . . . . . . . . . . . . .113
Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . .114
Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . .115
8.2 Introduction
This section describes the clock generator module (CGM). The CGM
generates the crystal clock signal, CGMXCLK, which operates at the
frequency of the crystal. The CGM also generates the base clock signal,
CGMOUT, from which the system integration module (SIM) derives the
system clocks. CGMOUT is based on either the crystal clock divided by
two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two.
The PLL is a frequency generator designed for use with 1-MHz to
8.4-MHz crystals or ceramic resonators. The PLL can generate an
8-MHz bus frequency without using a 32-MHz crystal.
8.3 Features
Features of the CGM include:
Phase-Locked Loop with Output Frequency in Integer Multiples of
the Crystal Reference
Programmable Hardware Voltage-Controlled Oscillator (VCO) for
Low-Jitter Operation
Automatic Bandwidth Control Mode for Low-Jitter Operation
Automatic Frequency Lock Detector
CPU Interrupt on Entry or Exit from Locked Condition