Advance Information
MC68HC08AS20
—
Rev. 4.1
308
Freescale Semiconductor
Read of a port pin which is in use by the ADC will return a logic 0 if the
corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value
in the port data latch is read.
NOTE:
Do not use ADC channel ATD14 when using the PTD6/ATD14/TCLK pin
as the clock input for the TIM.
19.4.2 Voltage Conversion
When the input voltage to the ADC equals V
REFH
(see
21.7 ADC
Characteristics
), the ADC converts the signal to $FF (full scale). If the
input voltage equals V
SSA
/V
REFL,
the ADC converts it to $00. Input
voltages between V
REFH
and V
SSA
/V
REFL
are a straight-line linear
conversion. All other input voltages will result in $FF if greater than
V
REFH
and $00 if less than V
SSA
/V
REFL
.
NOTE:
Input voltage should not exceed the analog supply voltages.
19.4.3 Conversion Time
Sixteen ADC internal clocks are required to perform one conversion. The
ADC starts a conversion on the first rising edge of the ADC internal clock
immediately following a write to the ADSCR. If the ADC internal clock is
selected to run at 1 MHz, then one conversion will take 16
μ
s to
complete. But since the ADC can run almost completely asynchronously
to the bus clock, (for example, the ADC is configured to derive its internal
clock from CGMXCLK and the bus clock is being derived from the PLL
within the CGM [CGMOUT]), this 16
μ
s conversion can take up to 17
μ
s
to complete. This worst-case could occur if the write to the ADSCR
happened directly after the rising edge of the ADC internal clock causing
the conversion to wait until the next rising edge of the ADC internal clock.
With a 1 MHz ADC internal clock the maximum sample rate is 59 kHz to
62 kHz. Refer to
21.7 ADC Characteristics
.
16 to 17 ADC Clock Cycles
ADC Clock Frequency
Conversion Time =
Number of Bus Cycles = Conversion Time x Bus Frequency