Input/Output (I/O) Section
MC68HC908GT16 MC68HC908GT8 MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
35
$0026
Timer 1 Channel 0
Register High (T1CH0H)
See page 236.
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 15
14
13
12
11
10
9
Bit 8
Indeterminate after reset
$0027
Timer 1 Channel 0
Register Low (T1CH0L)
See page 236.
Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after reset
$0028
Timer 1 Channel 1 Status and
Control Register (T1SC1)
See page 234.
CH1F
0
0
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
$0029
Timer 1 Channel 1
Register High (T1CH1H)
See page 236.
Bit 15
14
13
12
11
10
9
Bit 8
Indeterminate after reset
$002A
Timer 1 Channel 1
Register Low (T1CH1L)
See page 236.
Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after reset
0
TRST
0
12
$002B
Timer 2 Status and Control
Register (T2SC)
See page 231.
TOF
0
0
Bit 15
TOIE
TSTOP
0
PS2
PS1
PS0
0
1
0
0
0
9
0
$002C
Timer 2 Counter
Register High (T2CNTH)
See page 232.
14
13
11
10
Bit 8
0
0
6
0
5
0
4
0
3
0
2
0
1
0
$002D
Timer 2 Counter
Register Low (T2CNTL)
See page 232.
Bit 7
Bit 0
0
0
0
0
0
0
0
0
$002E
Timer 2 Counter Modulo
Register High (T2MODH)
See page 233.
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
$002F
Timer 2 Counter Modulo
Register Low (T2MODL)
See page 233.
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
$0030
Timer 2 Channel 0 Status and
Control Register (T2SC0)
See page 233.
CH0F
0
0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
$0031
Timer 2 Channel 0
Register High (T2CH0H)
See page 236.
Bit 15
14
13
12
11
10
9
Bit 8
Indeterminate after reset
$0032
Timer 2 Channel 0
Register Low (T2CH0L)
See page 236.
Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after reset
R = Reserved
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 7)