
Functional Description
MC68HC908GP32 MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
131
The monitor code has been updated from previous versions of the monitor code to allow enabling the PLL
to generate the internal clock, provided the reset vector is blank, when the device is being clocked by a
low-frequency crystal. This addition, which is enabled when IRQ is held low out of reset, is intended to
support serial communication/ programming at 9600 baud in monitor mode by stepping up the external
frequency (assumed to be 32.768 kHz) by a fixed amount to generate the desired internal frequency
(2.4576 MHz). Since this feature is enabled only when IRQ is held low out of reset, it cannot be used when
the reset vector is not blank because entry into monitor mode in this case requires VTST on IRQ.
15.3.1 Entering Monitor Mode
Table 15-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a POR and will allow communication at 9600 baud provided one of the following sets
of conditions is met:
1.
If $FFFE and $FFFF does not contain $FF (programmed state):
– The external clock is 4.9152 MHz with PTC3 low or 9.8304 MHz with PTC3 high
– IRQ = V
TST (PLL off)
2.
If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 9.8304 MHz
– IRQ = V
DD (this can be implemented through the internal IRQ pullup; PLL off)
3.
If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 32.768 kHz (crystal)
– IRQ = V
SS (this setting initiates the PLL to boost the external 32.768 kHz to an internal bus
frequency of 2.4576 MHz)
If VTST is applied to IRQ and PTC3 is low upon monitor mode entry (above condition set 1), the bus
frequency is a divide-by-two of the input clock. If PTC3 is high with VTST applied to IRQ upon monitor
mode entry, the bus frequency will be a divide-by-four of the input clock. Holding the PTC3 pin low when
entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if VTST is applied
to IRQ. In this event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input
directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at
maximum bus frequency.
If entering monitor mode without high voltage on IRQ (above condition set 2 or 3, where applied voltage
is either VDD or VSS), then all port C pin requirements and conditions, including the PTC3 frequency
divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit
programming.
NOTE
If the reset vector is blank and monitor mode is entered, the chip will see an
additional reset cycle after the initial POR reset. Once the part has been
programmed, the traditional method of applying a voltage, VTST, to IRQ
must be used to enter monitor mode.
The COP module is disabled in monitor mode based on these conditions:
If monitor mode was entered as a result of the reset vector being blank (above condition set 2 or
3), the COP is always disabled regardless of the state of IRQ or RST.
If monitor mode was entered with VTST on IRQ (condition set 1), then the COP is disabled as long
as VTST is applied to either IRQ or RST.