
Electrical Specifications
MC68HC08AZ32A Data Sheet, Rev. 2
290
Freescale Semiconductor
20.6 Control Timing
20.7 ADC Characteristics
Characteristic(1)
1. VDD = 5.0 Vdc ± 0.5 V, VSS = 0 Vdc, TA = –40°C to TA (MAX), unless otherwise noted.
Symbol
Min
Max
Unit
Bus operating frequency (4.5–5.5 V — VDD only)
fBus
—8.4
MHz
Internal clock period (1/fBus)
tCYC
119
—
ns
RST pulse width low
tRL
1.5
—
tCYC
IRQ interrupt pulse width low (edge triggered)
tILHI
1.5
—
tCYC
IRQ Interrupt Pulse Period
tILIL
Note 3
—
tCYC
16-bit timer
Input capture pulse width(2)
Input capture period
Input clock pulse width
tTH, tTL
tTLTL
tTCH, tTCL
2
Note(3)
(1/fOP) + 5
3. The minimum period tTLTL or tILIL should not be less than the number of cycles it takes to execute the capture interrupt
service routine plus t CYC.
—
tCYC
ns
MSCAN wakeup filter pulse width(4)
4. The minimum pulse width to wake up the MSCAN module is guaranteed by design but not tested.
tWUP
25
s
Characteristic(1)
1. VDD = 5.0 Vdc ± 0.5 V, VSS = 0 Vdc, VDDA/VDDAREF = 5.0 Vdc ± 0.5 V, VSSA = 0 Vdc, VREFH = 5.0 Vdc ± 0.5 V
Min
Max
Unit
Comments
Resolution
8
Bits
Absolute accuracy
(VREFL = 0 V, VDDA = VREFH = 5 V ± 0.5 V)
–1
+1
LSB
Includes quantization
Conversion range
VREFL
VREFH
V
VREFL = VSSA
Powerup time
16
17
s
Conversion time period
Input leakage(2) (ports B and D)
2. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
– 1
1
A
Input leakage(3) (ports B and D)
3. When subjected to a Human Body Model (HBM) ESD event as specified in AEC Q100-002 these pins may exhibit recov-
erable leakage values within the specification indicated.
–10
10
A
Conversion Time
16
17
ADC clock cycles
Includes sampling time
Monotonicity
Inherent within total error
Zero input reading
00
01
Hex
VIN = VREFL
Full-scale reading
FE
FF
Hex
VIN = VREFH
Sample time(4)
4. Source impedances greater than 10 k
adversely affect internal RC charging time during input sampling.
5
—
ADC clock cycles
Input capacitance
—
8
pF
Not tested
ADC internal clock
500 k
1.048 M
Hz
Tested only at 1 MHz
Analog input voltage
VREFL
VREFH
V