
Data Sheet
MC68HC08AS32 — Rev. 4.1
172
Freescale Semiconductor
12.8.2 SCI Control Register 2
SCI control register 2:
Enables the following CPU interrupt requests:
–
Enables the SCTE bit to generate transmitter CPU interrupt requests
–
Enables the TC bit to generate transmitter CPU interrupt requests
–
Enables the SCRF bit to generate receiver CPU interrupt requests
–
Enables the IDLE bit to generate receiver CPU interrupt requests
Enables the transmitter
Enables the receiver
Enables SCI wakeup
Transmits SCI break characters
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter CPU
interrupt requests. Reset clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt requests
0 = SCTE not enabled to generate CPU interrupt requests
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt
requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt
requests. Reset clears the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt requests
0 = SCRF not enabled to generate CPU interrupt requests
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt
requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a preamble of 10
or 11 logic 1s from the transmit shift register to the PTE0/TxD pin. If software
Address:
$0014
Bit 7
654321
Bit 0
Read:
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
Write:
Reset:
00000000
Figure 12-9. SCI Control Register 2 (SCC2)