Clock Generator Module (CGM)
CGM During Break Interrupts
MC68HC08AS32
—
Rev. 3.0
Advance Information
MOTOROLA
Clock Generator Module (CGM)
115
L
G
R
8.9 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See
9.8.3 SIM Break Flag Control
Register
.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
ToprotectthePLLFbitduringthebreakstate,writealogic0totheBCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the
PLLF bit.
8.10 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensure the highest stability and lowest acquisition/lock times.
8.10.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the
reaction time, within specified tolerances, of the system to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance usually is specified as a percent of the
step input or when the output settles to the desired value plus or minus
a percent of the frequency change. Therefore, the reaction time is
constant in this definition, regardless of the size of the step input. For
example, consider a system with a 5% acquisition time tolerance. If a
command instructs the system to change from 0 Hz to 1 MHz, the
acquisition time is the time taken for the frequency to reach
1 MHz
±
50 kHz. 50 kHz = 5% of the 1-MHz step input. If the system is
operatingat1 MHzandsuffersa–100-kHznoisehit,theacquisitiontime